/linux-master/drivers/gpu/drm/radeon/ |
H A D | trinity_smc.c | 66 WREG32_SMC(SMU_SCRATCH0, 1); 68 WREG32_SMC(SMU_SCRATCH0, 0); 75 WREG32_SMC(SMU_SCRATCH0, n); 82 WREG32_SMC(SMU_SCRATCH0, n);
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H A D | si_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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H A D | ci_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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H A D | trinity_dpm.c | 335 WREG32_SMC(GFX_POWER_GATING_CNTL, value); 459 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); 477 WREG32_SMC(PM_I_CNTL_1, value); 482 WREG32_SMC(SMU_S_PG_CNTL, value); 486 WREG32_SMC(SMU_S_PG_CNTL, value); 490 WREG32_SMC(PM_I_CNTL_1, value); 551 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); 561 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); 573 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); 585 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_ [all...] |
H A D | ci_dpm.c | 570 WREG32_SMC(config_regs->offset, data); 860 WREG32_SMC(CG_THERMAL_INT, tmp); 867 WREG32_SMC(CG_THERMAL_CTRL, tmp); 884 WREG32_SMC(CG_THERMAL_INT, thermal_int); 893 WREG32_SMC(CG_THERMAL_INT, thermal_int); 920 WREG32_SMC(CG_FDO_CTRL2, tmp); 924 WREG32_SMC(CG_FDO_CTRL2, tmp); 1098 WREG32_SMC(CG_FDO_CTRL0, tmp); 1175 WREG32_SMC(CG_TACH_CTRL, tmp); 1191 WREG32_SMC(CG_FDO_CTRL [all...] |
H A D | kv_dpm.c | 190 WREG32_SMC(config_regs->offset, data); 367 WREG32_SMC(CG_FTV_0, 0x3FFFC100); 372 WREG32_SMC(CG_FTV_0, 0); 490 WREG32_SMC(GENERAL_PWRMGT, tmp); 507 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 516 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 1023 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); 2244 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); 2268 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
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H A D | cik.c | 9422 WREG32_SMC(cntl_reg, tmp); 9469 WREG32_SMC(CG_ECLK_CNTL, tmp); 9742 WREG32_SMC(THM_CLK_CNTL, data); 9748 WREG32_SMC(MISC_CLK_CTRL, data); 9753 WREG32_SMC(CG_CLKPIN_CNTL, data); 9758 WREG32_SMC(CG_CLKPIN_CNTL_2, data); 9764 WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
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H A D | si.c | 5446 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); 5447 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); 5458 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); 5459 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
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H A D | radeon.h | 2519 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro 2553 WREG32_SMC(reg, tmp_); \
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H A D | si_dpm.c | 2700 WREG32_SMC(offset, data);
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_smc.c | 117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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H A D | kv_dpm.c | 391 WREG32_SMC(local_cac_reg->cntl, data); 431 WREG32_SMC(config_regs->offset, data); 522 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); 523 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); 526 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); 527 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); 530 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); 531 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); 534 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); 535 WREG32_SMC(ixLCAC_MC2_OVR_VA [all...] |
H A D | si_dpm.c | 2860 WREG32_SMC(offset, data); 7561 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7566 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7578 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7583 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | vi.c | 620 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 631 WREG32_SMC(ixROM_CNTL, rom_cntl); 1002 WREG32_SMC(cntl_reg, tmp); 1092 WREG32_SMC(reg_ctrl, tmp); 1192 WREG32_SMC(ixTHM_CLK_CNTL, data); 1201 WREG32_SMC(ixMISC_CLK_CTRL, data); 1206 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1211 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1217 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1847 WREG32_SMC(ixCGTT_ROM_CLK_CTRL [all...] |
H A D | cik.c | 997 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 1008 WREG32_SMC(ixROM_CNTL, rom_cntl); 1468 WREG32_SMC(cntl_reg, tmp); 1517 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 1797 WREG32_SMC(ixTHM_CLK_CNTL, data); 1805 WREG32_SMC(ixMISC_CLK_CTRL, data); 1810 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1815 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); 1821 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
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H A D | amdgpu_cgs.c | 94 return WREG32_SMC(index, value);
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H A D | amdgpu.h | 1285 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro 1318 WREG32_SMC(_Reg, tmp); \
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H A D | vce_v4_0.c | 911 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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H A D | uvd_v7_0.c | 1722 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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H A D | amdgpu_debugfs.c | 848 WREG32_SMC(*pos, value);
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H A D | gfx_v8_0.c | 802 WREG32_SMC(ixCG_ACLK_CNTL, data);
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