/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfxhub_v1_0.c | 197 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 198 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 202 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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H A D | mmhub_v1_0.c | 183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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H A D | gfxhub_v1_2.c | 246 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 247 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 250 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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H A D | mmhub_v1_8.c | 251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 252 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 255 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 256 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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H A D | mmhub_v1_7.c | 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 202 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 205 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 206 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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H A D | gmc_v7_0.c | 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
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H A D | gmc_v8_0.c | 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
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H A D | sid.h | 386 #define VM_L2_CNTL3 0x502 macro
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv770.c | 911 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 957 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 988 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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H A D | rv770d.h | 650 #define VM_L2_CNTL3 0x1408 macro
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H A D | ni.c | 1275 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1354 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
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H A D | nid.h | 120 #define VM_L2_CNTL3 0x1408 macro
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H A D | r600.c | 1146 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1198 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1238 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
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H A D | sid.h | 385 #define VM_L2_CNTL3 0x1408 macro
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H A D | cikd.h | 503 #define VM_L2_CNTL3 0x1408 macro
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H A D | evergreen.c | 2417 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 2470 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 2500 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
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H A D | r600d.h | 595 #define VM_L2_CNTL3 0x1408 macro
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H A D | evergreend.h | 1158 #define VM_L2_CNTL3 0x1408 macro
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H A D | si.c | 4292 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 4378 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
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H A D | cik.c | 5446 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 5563 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
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