Searched refs:VM_L2_CNTL3 (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c197 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
198 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
202 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
H A Dmmhub_v1_0.c183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
H A Dgfxhub_v1_2.c246 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
247 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
250 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
H A Dmmhub_v1_8.c251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
252 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
255 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
256 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
H A Dmmhub_v1_7.c201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
202 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
205 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
206 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
H A Dgmc_v7_0.c639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
H A Dgmc_v8_0.c854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
H A Dsid.h386 #define VM_L2_CNTL3 0x502 macro
/linux-master/drivers/gpu/drm/radeon/
H A Drv770.c911 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
957 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
988 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
H A Drv770d.h650 #define VM_L2_CNTL3 0x1408 macro
H A Dni.c1275 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1354 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
H A Dnid.h120 #define VM_L2_CNTL3 0x1408 macro
H A Dr600.c1146 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1198 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1238 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
H A Dsid.h385 #define VM_L2_CNTL3 0x1408 macro
H A Dcikd.h503 #define VM_L2_CNTL3 0x1408 macro
H A Devergreen.c2417 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2470 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2500 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
H A Dr600d.h595 #define VM_L2_CNTL3 0x1408 macro
H A Devergreend.h1158 #define VM_L2_CNTL3 0x1408 macro
H A Dsi.c4292 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4378 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
H A Dcik.c5446 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5563 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

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