Searched refs:UVD_VCPU_CNTL__BLK_RST_MASK (Results 1 - 13 of 13) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c855 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
1047 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1075 UVD_VCPU_CNTL__BLK_RST_MASK, local
1076 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1079 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1209 UVD_VCPU_CNTL__BLK_RST_MASK, local
1210 ~UVD_VCPU_CNTL__BLK_RST_MASK);
H A Dvcn_v5_0_0.c638 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
776 ~UVD_VCPU_CNTL__BLK_RST_MASK);
804 UVD_VCPU_CNTL__BLK_RST_MASK, local
805 ~UVD_VCPU_CNTL__BLK_RST_MASK);
808 ~UVD_VCPU_CNTL__BLK_RST_MASK);
940 UVD_VCPU_CNTL__BLK_RST_MASK, local
941 ~UVD_VCPU_CNTL__BLK_RST_MASK);
H A Dvcn_v4_0_3.c748 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
1133 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1153 UVD_VCPU_CNTL__BLK_RST_MASK, local
1154 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1158 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
1300 UVD_VCPU_CNTL__BLK_RST_MASK, local
1301 ~UVD_VCPU_CNTL__BLK_RST_MASK);
H A Dvcn_v3_0.c969 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
1189 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1206 UVD_VCPU_CNTL__BLK_RST_MASK, local
1207 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1210 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1570 UVD_VCPU_CNTL__BLK_RST_MASK, local
1571 ~UVD_VCPU_CNTL__BLK_RST_MASK);
H A Dvcn_v4_0.c941 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
1136 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1163 UVD_VCPU_CNTL__BLK_RST_MASK, local
1164 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1167 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1547 UVD_VCPU_CNTL__BLK_RST_MASK, local
1548 ~UVD_VCPU_CNTL__BLK_RST_MASK);
H A Dvcn_v2_5.c846 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
1066 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1086 UVD_VCPU_CNTL__BLK_RST_MASK, local
1087 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1090 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1427 UVD_VCPU_CNTL__BLK_RST_MASK, local
1428 ~UVD_VCPU_CNTL__BLK_RST_MASK);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_sh_mask.h3774 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
H A Dvcn_4_0_5_sh_mask.h3939 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
H A Dvcn_4_0_0_sh_mask.h4072 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
H A Dvcn_4_0_3_sh_mask.h4111 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
[all...]
H A Dvcn_2_5_sh_mask.h2765 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
H A Dvcn_2_6_0_sh_mask.h118 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro
H A Dvcn_3_0_0_sh_mask.h3824 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L macro

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