Searched refs:SKL_DPLL1_CFGCR2 (Results 1 - 2 of 2) sorted by relevance

/haiku/src/add-ons/accelerants/intel_extreme/
H A DPipes.cpp571 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8));
583 write32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8,
590 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8);
603 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8));
/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h895 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) macro

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