Searched refs:SKL_DPLL1_CFGCR1 (Results 1 - 2 of 2) sorted by relevance

/haiku/src/add-ons/accelerants/intel_extreme/
H A DPipes.cpp569 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8));
579 write32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8,
589 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8);
601 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8));
/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h894 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) macro

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