Searched refs:Rn (Results 1 - 11 of 11) sorted by last modified time

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); local
473 assert(isARMLowRegister(Rn));
481 .addReg(Rn, RegState::Define)
482 .addReg(Rn)
H A DARMBaseInstrInfo.cpp3462 Register Rn = MI.getOperand(2).getReg(); local
3467 return (Rt == Rn) ? 3 : 2;
3488 Register Rn = MI.getOperand(3).getReg(); local
3493 return (Rt == Rn) ? 4 : 3;
3498 Register Rn = MI.getOperand(3).getReg(); local
3499 return (Rt == Rn) ? 4 : 3;
3535 Register Rn = MI.getOperand(2).getReg(); local
3536 return (Rt == Rn) ? 3 : 2;
3794 // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops
3795 // (outs GPR:$wb), (ins GPR:$Rn,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp933 // [Rn, Rm]
935 // {2-0} = Rn
938 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local
940 return (Rm << 3) | Rn;
991 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1065 // {6-3} Rn
1070 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); local
1075 return (Rn << 3) | Qm;
1124 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1256 unsigned Rn
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1558 // Writeback not allowed if Rn is in the target list.
1652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1827 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887 if (writeback && (Rn == 15 || Rn == Rt))
1932 unsigned Rn local
1977 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2167 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2198 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2220 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2474 unsigned Rn = fieldFromInstruction(Insn, 0, 4); local
2502 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2552 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
2570 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
2590 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
2688 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3015 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3284 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3379 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3414 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3609 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3691 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3706 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3738 unsigned Rn = fieldFromInstruction(Val, 6, 4); local
3768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4135 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
4151 unsigned Rn = fieldFromInstruction(Val, 8, 4); local
4166 unsigned Rn = fieldFromInstruction(Val, 8, 4); local
4208 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
4256 unsigned Rn = fieldFromInstruction(Val, 8, 3); local
4273 unsigned Rn = fieldFromInstruction(Val, 8, 4); local
4291 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4351 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
4436 unsigned Rn = fieldFromInstruction(Insn, 3, 4); local
4514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4875 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4900 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5162 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5376 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5532 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5638 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
5816 unsigned Rn = fieldFromInstruction(Val, 16, 4); local
6014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
6322 unsigned Rn = fieldFromInstruction(Val, 16, 4); local
6339 DecodeMVE_MEM_pre( MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) argument
6607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
6624 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5555 // If we have a three-operand form, make sure to set Rn to be the operand
7290 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); local
7292 if (Rn == Rt || Rn == Rt2) {
7479 // Rt must be different from Rn.
7481 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
7483 if (Rt == Rn)
7512 // Rt must be different from Rn.
7514 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
7516 if (Rt == Rn)
7589 unsigned Rn = Inst.getOperand(0).getReg(); local
9935 unsigned Rn = Inst.getOperand(0).getReg(); local
9959 unsigned Rn = Inst.getOperand(0).getReg(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp846 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local
851 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
854 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
937 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
965 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
986 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1032 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1083 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1093 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1151 DecodeGPR64spRegisterClass(Inst, Rn, Add
1291 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1374 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1508 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1565 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1671 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3975 unsigned Rn = Inst.getOperand(3).getReg(); local
3976 if (RI->isSubRegisterEq(Rn, Rt))
3979 if (RI->isSubRegisterEq(Rn, Rt2))
4021 unsigned Rn = Inst.getOperand(3).getReg(); local
4022 if (RI->isSubRegisterEq(Rn, Rt))
4025 if (RI->isSubRegisterEq(Rn, Rt2))
4053 unsigned Rn = Inst.getOperand(2).getReg(); local
4054 if (RI->isSubRegisterEq(Rn, Rt))
4072 unsigned Rn = Inst.getOperand(2).getReg(); local
4073 if (RI->isSubRegisterEq(Rn, R
4088 unsigned Rn = Inst.getOperand(2).getReg(); local
4102 unsigned Rn = Inst.getOperand(3).getReg(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp593 // integer n = UInt(Rn);
632 const uint32_t Rn = Bits32(opcode, 9, 5); local
638 const uint32_t n = UInt(Rn);
712 uint32_t Rn = Bits32(opcode, 9, 5); local
715 integer n = UInt(Rn);
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1505 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
1518 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1531 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1897 // if Rn == '1111' then SEE ADR;
2490 Rn; // This function assumes Rn is the SP, but we should verify that. local
2499 Rn = Bits32(opcode, 19, 16);
2501 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
2508 if (wback && ((Rn
2963 uint32_t Rn; // the base register which contains the address of the table of local
3113 uint64_t Rn = local
3165 uint32_t Rd, Rn; local
3231 uint32_t Rd, Rn, Rm; local
3313 uint32_t Rn; // the first operand local
3361 uint32_t Rn; // the first operand local
3426 uint32_t Rn; // the first operand local
3478 uint32_t Rn; // the first operand local
3856 uint32_t Rn; // the first operand register local
4108 addr_t Rn = ReadCoreReg(n, &success); local
4247 addr_t Rn = local
4359 addr_t Rn = local
4452 uint32_t Rn; // the base register local
4791 addr_t Rn = ReadCoreReg(n, &success); local
4938 addr_t Rn = local
5062 addr_t Rn = ReadCoreReg(n, &success); local
5830 uint32_t Rd, Rn; local
5900 uint32_t Rd, Rn, Rm; local
6047 uint32_t Rd, Rn; local
6123 uint32_t Rd, Rn, Rm; local
6212 uint32_t Rd, Rn; local
6288 uint32_t Rd, Rn, Rm; local
6794 uint32_t Rn = local
7176 uint32_t Rn = local
7457 uint64_t Rn = local
7613 uint64_t Rn = ReadCoreReg(n, &success); local
7862 uint64_t Rn = local
8012 uint64_t Rn = local
8772 uint64_t Rn = local
8854 uint32_t Rd, Rn; local
8933 uint32_t Rd, Rn, Rm; local
9023 uint32_t Rd, Rn; local
9100 uint32_t Rd, Rn, Rm; local
9188 uint32_t Rn; // the first operand local
9261 uint32_t Rn; // the first operand local
9339 uint32_t Rn; // the first operand local
9399 uint32_t Rn; // the first operand local
9468 uint32_t Rn; // the first operand local
9537 uint32_t Rn; // the first operand local
9617 uint32_t Rn; // the first operand local
9711 uint32_t Rn; // the first operand local
9782 uint32_t Rn; local
9842 uint32_t Rn, Rm; local
9907 uint32_t Rn; local
9967 uint32_t Rn, Rm; local
10413 uint32_t Rn = ReadCoreReg(n, &success); local
10508 uint32_t Rn = ReadCoreReg(n, &success); local
10601 uint32_t Rn = ReadCoreReg(n, &success); local
10746 uint32_t Rn = ReadCoreReg(n, &success); local
10869 uint32_t Rn = ReadCoreReg(n, &success); local
11024 uint32_t Rn = ReadCoreReg(n, &success); local
11159 uint32_t Rn = ReadCoreReg(n, &success); local
11333 uint32_t Rn = ReadCoreReg(n, &success); local
11528 uint32_t Rn = ReadCoreReg(n, &success); local
11686 uint32_t Rn = ReadCoreReg(n, &success); local
11821 uint32_t Rn = ReadCoreReg(n, &success); local
11984 uint32_t Rn = ReadCoreReg(n, &success); local
12151 uint32_t Rn = ReadCoreReg(n, &success); local
12317 uint32_t Rn = ReadCoreReg(n, &success); local
12484 uint32_t Rn = ReadCoreReg(n, &success); local
12609 uint32_t Rn = ReadCoreReg(n, &success); local
12759 uint32_t Rn = ReadCoreReg(n, &success); local
[all...]
/freebsd-11-stable/contrib/binutils/gas/config/
H A Dtc-arm.c1854 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
4568 [Rn, #offset] .reg=Rn .reloc.exp=offset
4569 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4570 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4577 [Rn], #offset .reg=Rn .reloc.exp=offset
4578 [Rn],
6531 unsigned Rn = inst.operands[2].reg; local
8428 int Rd, Rn; local
8444 int Rd, Rs, Rn; local
8669 int Rd, Rs, Rn; local
8752 int Rd, Rs, Rn; local
9350 int Rn; local
[all...]
/freebsd-11-stable/contrib/binutils/opcodes/
H A Darm-dis.c3442 unsigned int Rn = (given & 0x000f0000) >> 16;
3450 func (stream, "[%s", arm_regnames[Rn]);
3453 else if (Rn == 15) /* 12-bit negative immediate offset */
3509 if (Rn == 15)
3523 unsigned int Rn = (given & 0x000f0000) >> 16;
3526 func (stream, "[%s", arm_regnames[Rn]);
3441 unsigned int Rn = (given & 0x000f0000) >> 16; local
3522 unsigned int Rn = (given & 0x000f0000) >> 16; local

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