gas/config/tc-arm.c

1854               first_error (_("don't use Rn-Rm syntax with non-unit stride"));
4568    [Rn, #offset]       .reg=Rn .reloc.exp=offset
4569    [Rn, +/-Rm]	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4570    [Rn, +/-Rm, shift]  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4577    [Rn], #offset       .reg=Rn .reloc.exp=offset
4578    [Rn], +/-Rm	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4579    [Rn], +/-Rm, shift  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4584    [Rn], {option}      .reg=Rn .imm=option .immisreg=0
4588    [Rn]{!}	       shorthand for [Rn,#0]{!}
4757 	  /* [Rn], {expr} - unindexed, with option */
4817      bare [Rn]{!}, which is shorthand for [Rn,#0]{!}.  */
5194           /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5223              Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
5292           /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
6535   unsigned Rn = inst.operands[2].reg;
6538     constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6539 		_("Rn must not overlap other operands"));
6542   inst.instruction |= Rn << 16;
6839    MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6849    Result unpredicatable if Rd or Rn is R15.  */
7027   /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
7028      reject [Rn,...].  */
7058   /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
7059      reject [Rn,...].  */
7301    PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7303    Error if Rd, Rn or Rm are R15.  */
7389    Error if Rn is R15.	*/
7489    SMLAxy{cond} Rd,Rm,Rs,Rn
7490    SMLAWy{cond} Rd,Rm,Rs,Rn
7605    SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7913 	 [Rn]{!}.  The instruction does not really support stacking or
8438   int Rd, Rn;
8441   Rn = inst.operands[1].reg;
8444   inst.instruction |= (Rn << 16) | (Rd << 8);
8454   int Rd, Rs, Rn;
8547 	  Rn = inst.operands[2].reg;
8551 	      if (Rd > 7 || Rs > 7 || Rn > 7)
8560 		  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8571 		      inst.instruction |= Rn << 3;
8575 		  else if (Rd == Rn)
8613       Rn = inst.operands[2].reg;
8616       /* We now have Rd, Rs, and Rn set to registers.  */
8617       if (Rd > 7 || Rs > 7 || Rn > 7)
8625 	    inst.instruction |= Rn << 3;
8626 	  else if (Rn == Rd)
8635 	  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8679   int Rd, Rs, Rn;
8685   Rn = inst.operands[2].reg;
8709 	  if (Rd > 7 || Rn > 7 || Rs > 7)
8721 	      inst.instruction |= Rn << 3;
8744       constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8750       inst.instruction |= Rn << 3;
8762   int Rd, Rs, Rn;
8768   Rn = inst.operands[2].reg;
8792 	  if (Rd > 7 || Rn > 7 || Rs > 7)
8805 		  inst.instruction |= Rn << 3;
8808 	      if (Rd == Rn)
8836       constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8842 	inst.instruction |= Rn << 3;
8843       else if (Rd == Rn)
9360   int Rn;
9380 	  Rn = inst.operands[1].reg;
9384 	      /* [Rn, Ri] */
9385 	      if (Rn <= 7 && inst.operands[1].imm <= 7)
9388 	  else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9390 		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9391 		   || (Rn == REG_SP && opcode == T_MNEM_str))
9393 	      /* [Rn, #const] */
9394 	      if (Rn > 7)
9396 		  if (Rn == REG_PC)
9436       /* Only [Rn,Rm] is acceptable.  */
10287       if (inst.operands[2].isreg)  /* Rd, {Rs,} Rn */
11596   |  U  |x |D  |size | Rn  | Rd  |x x x x|N|Q|M|x| Rm |
12922   |  U  |x |D |size | Rn  | Rd  |x x x x|N|x|M|x| Rm |
13118    (Register operations, which are VORR with Rm = Rn.)
13124      5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13128      7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13142     15. VMOV <Sd>, <Se>, <Rn>, <Rm>