Searched refs:Read32 (Results 1 - 12 of 12) sorted by relevance

/haiku/src/add-ons/accelerants/radeon_hd/
H A Dbios.cpp40 biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
41 biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
43 biosScratch2 = Read32(OUT, RADEON_BIOS_2_SCRATCH);
44 biosScratch6 = Read32(OUT, RADEON_BIOS_6_SCRATCH);
72 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
74 | Read32(OUT, EVERGREEN_CRTC_CONTROL
80 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
82 | Read32(OUT, EVERGREEN_CRTC_CONTROL
84 | Read32(OUT, EVERGREEN_CRTC_CONTROL
86 | Read32(OU
[all...]
H A Dgpu.cpp100 if ((Read32(OUT, GRBM_STATUS) & GUI_ACTIVE) == 0)
160 if ((Read32(OUT, GRBM_STATUS) & grbmBusyMask) != 0
161 || (Read32(OUT, GRBM_STATUS2) & grbm2BusyMask) != 0) {
176 Read32(OUT, GRBM_SOFT_RESET);
184 Read32(OUT, GRBM_SOFT_RESET);
212 Read32(OUT, GRBM_SOFT_RESET);
216 Read32(OUT, GRBM_SOFT_RESET);
273 gpuState->d1vgaControl = Read32(OUT, AVIVO_D1VGA_CONTROL);
274 gpuState->d2vgaControl = Read32(OUT, AVIVO_D2VGA_CONTROL);
275 gpuState->vgaRenderControl = Read32(OU
[all...]
H A Dmode.cpp242 Read32(CRT, AVIVO_D1CRTC_STATUS));
244 Read32(CRT, AVIVO_D2CRTC_STATUS));
246 Read32(CRT, AVIVO_D1CRTC_CONTROL));
248 Read32(CRT, AVIVO_D2CRTC_CONTROL));
250 Read32(CRT, AVIVO_D1GRPH_ENABLE));
252 Read32(CRT, AVIVO_D2GRPH_ENABLE));
254 Read32(CRT, AVIVO_D1SCL_SCALER_ENABLE));
256 Read32(CRT, AVIVO_D2SCL_SCALER_ENABLE));
258 Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL));
260 Read32(CR
[all...]
H A Dconnector.cpp46 buffer = Read32(OUT, info->i2c.sclMaskReg);
52 buffer = Read32(OUT, info->i2c.sclAReg) & ~info->i2c.sclAMask;
54 buffer = Read32(OUT, info->i2c.sdaAReg) & ~info->i2c.sdaAMask;
59 buffer = Read32(OUT, info->i2c.sclEnReg) & ~info->i2c.sclEnMask;
61 buffer = Read32(OUT, info->i2c.sdaEnReg) & ~info->i2c.sdaEnMask;
65 buffer = Read32(OUT, info->i2c.sclMaskReg);
72 Read32(OUT, info->i2c.sclMaskReg);
75 buffer = Read32(OUT, info->i2c.sdaMaskReg);
82 Read32(OUT, info->i2c.sdaMaskReg);
91 uint32 scl = Read32(OU
[all...]
H A Dencoder.cpp1185 uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
1195 uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
1207 uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
1219 uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
1248 uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
1776 uint32 biosScratch3 = Read32(OUT, R600_SCRATCH_REG3);
1825 uint32 biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
2111 uint32 biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
H A Daccelerant.h251 Read32(uint32 subsystem, uint32 offset) function
H A Ddisplay.cpp878 = Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);
886 uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);
/haiku/src/system/boot/platform/riscv/
H A DFwCfg.cpp66 uint32_t Read32() {uint32_t val; ReadBytes((uint8_t*)&val, sizeof(val)); return val;} function in namespace:FwCfg
73 uint32_t count = B_BENDIAN_TO_HOST_INT32(Read32());
94 uint32_t count = B_BENDIAN_TO_HOST_INT32(Read32());
143 dprintf("fwCfgSelectSignature: 0x%08" B_PRIx32 "\n", Read32());
145 dprintf("fwCfgSelectId: : 0x%08" B_PRIx32 "\n", Read32());
/haiku/src/add-ons/kernel/drivers/audio/hda/
H A Ddriver.h98 uint32 Read32(uint32 reg) function in struct:hda_controller
136 uint32 temp = Read32(reg);
196 uint32 Read32(uint32 reg) function in struct:hda_stream
198 return controller->Read32(HDAC_STREAM_BASE + offset + reg);
H A Dhda_controller.cpp207 value = base->Read32(reg);
304 : stream->Read32(HDAC_STREAM_POSITION);
309 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION);
355 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS);
449 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL);
490 control = controller->Read32(HDAC_GLOBAL_CONTROL);
506 control = controller->Read32(HDAC_GLOBAL_CONTROL);
519 control = controller->Read32(HDAC_GLOBAL_CONTROL);
769 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)
795 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTRO
[all...]
/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Ddriver.h78 uint32 Read32(uint32 reg) function in struct:geode_controller
145 uint32 Read32(uint32 reg) function in struct:geode_stream
147 return controller->Read32(ACC_BM0_CMD + offset + reg);
H A Dgeode_controller.cpp43 && (controller->Read32(ACC_CODEC_CNTL) & ACC_CODEC_CNTL_CMD_NEW); i--)
67 v = controller->Read32(ACC_CODEC_STATUS);
119 position = controller->Read32(ACC_BM0_PNTR + stream->dma_offset);

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