1/*
2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Ithamar Adema, ithamar AT unet DOT nl
7 *		Axel D��rfler, axeld@pinc-software.de
8 */
9#ifndef _HDA_H_
10#define _HDA_H_
11
12#include <KernelExport.h>
13#include <Drivers.h>
14#include <PCI.h>
15
16#include <string.h>
17#include <stdlib.h>
18
19#define DEVFS_PATH_FORMAT	"audio/hmulti/hda/%" B_PRIu32
20#include <hmulti_audio.h>
21
22#include "hda_controller_defs.h"
23#include "hda_codec_defs.h"
24
25#define MAX_CARDS				4
26
27#define HDA_MAX_AUDIO_GROUPS	15
28#define HDA_MAX_CODECS			15
29#define HDA_MAX_STREAMS			16
30#define MAX_CODEC_RESPONSES		16
31#define MAX_CODEC_UNSOL_RESPONSES 16
32#define MAX_INPUTS				32
33#define MAX_IO_WIDGETS			8
34#define MAX_ASSOCIATIONS		32
35#define MAX_ASSOCIATION_PINS	16
36
37#define STREAM_MAX_BUFFERS	10
38#define STREAM_MIN_BUFFERS	2
39
40
41enum {
42	STREAM_PLAYBACK,
43	STREAM_RECORD
44};
45
46struct hda_codec;
47struct hda_stream;
48struct hda_multi;
49
50/*!	This structure describes a single HDA compliant
51	controller. It contains a list of available streams
52	for use by the codecs contained, and the messaging queue
53	(verb/response) buffers for communication.
54*/
55struct hda_controller {
56	struct pci_info	pci_info;
57	int32			opened;
58	const char*		devfs_path;
59
60	area_id			regs_area;
61	vuint8*			regs;
62	uint32			irq;
63	bool			msi;
64	bool			dma_snooping;
65	bool			is_64_bit;
66
67	uint16			codec_status;
68	uint32			num_input_streams;
69	uint32			num_output_streams;
70	uint32			num_bidir_streams;
71
72	uint32			corb_length;
73	uint32			rirb_length;
74	uint32			rirb_read_pos;
75	uint32			corb_write_pos;
76	area_id			corb_rirb_pos_area;
77	corb_t*			corb;
78	rirb_t*			rirb;
79	uint32*			stream_positions;
80
81	hda_codec*		codecs[HDA_MAX_CODECS + 1];
82	hda_codec*		active_codec;
83	uint32			num_codecs;
84
85	hda_stream*		streams[HDA_MAX_STREAMS];
86	sem_id			buffer_ready_sem;
87
88	uint8 Read8(uint32 reg)
89	{
90		return *(regs + reg);
91	}
92
93	uint16 Read16(uint32 reg)
94	{
95		return *(vuint16*)(regs + reg);
96	}
97
98	uint32 Read32(uint32 reg)
99	{
100		return *(vuint32*)(regs + reg);
101	}
102
103	void Write8(uint32 reg, uint8 value)
104	{
105		*(regs + reg) = value;
106	}
107
108	void Write16(uint32 reg, uint16 value)
109	{
110		*(vuint16*)(regs + reg) = value;
111	}
112
113	void Write32(uint32 reg, uint32 value)
114	{
115		*(vuint32*)(regs + reg) = value;
116	}
117
118	void ReadModifyWrite8(uint32 reg, uint8 mask, uint8 value)
119	{
120		uint8 temp = Read8(reg);
121		temp &= ~mask;
122		temp |= value;
123		Write8(reg, temp);
124	}
125
126	void ReadModifyWrite16(uint32 reg, uint16 mask, uint16 value)
127	{
128		uint16 temp = Read16(reg);
129		temp &= ~mask;
130		temp |= value;
131		Write16(reg, temp);
132	}
133
134	void ReadModifyWrite32(uint32 reg, uint32 mask, uint32 value)
135	{
136		uint32 temp = Read32(reg);
137		temp &= ~mask;
138		temp |= value;
139		Write32(reg, temp);
140	}
141};
142
143/*!	This structure describes a single stream of audio data,
144	which is can have multiple channels (for stereo or better).
145*/
146struct hda_stream {
147	uint32		id;					/* HDA controller stream # */
148	uint32		offset;				/* HDA I/O/B descriptor offset */
149	bool		running;
150	spinlock	lock;				/* Write lock */
151	uint32		type;
152
153	hda_controller* controller;
154
155	uint32		pin_widget;			/* PIN Widget ID */
156	uint32		io_widgets[MAX_IO_WIDGETS];	/* Input/Output Converter Widget ID */
157	uint32		num_io_widgets;
158
159	uint32		sample_rate;
160	uint32		sample_format;
161
162	uint32		num_buffers;
163	uint32		num_channels;
164	uint32		buffer_length;	/* size of buffer in samples */
165	uint32		buffer_size;	/* actual (aligned) size of buffer in bytes */
166	uint32		sample_size;
167	uint8*		buffers[STREAM_MAX_BUFFERS];
168					/* Virtual addresses for buffer */
169	phys_addr_t	physical_buffers[STREAM_MAX_BUFFERS];
170					/* Physical addresses for buffer */
171
172	volatile bigtime_t	real_time;
173	volatile uint64		frames_count;
174	uint32				last_link_frame_position;
175	volatile int32		buffer_cycle;
176
177	uint32		rate, bps;			/* Samplerate & bits per sample */
178
179	area_id		buffer_area;
180	area_id		buffer_descriptors_area;
181	phys_addr_t	physical_buffer_descriptors;	/* BDL physical address */
182
183	int32		incorrect_position_count;
184	bool		use_dma_position;
185
186	uint8 Read8(uint32 reg)
187	{
188		return controller->Read8(HDAC_STREAM_BASE + offset + reg);
189	}
190
191	uint16 Read16(uint32 reg)
192	{
193		return controller->Read16(HDAC_STREAM_BASE + offset + reg);
194	}
195
196	uint32 Read32(uint32 reg)
197	{
198		return controller->Read32(HDAC_STREAM_BASE + offset + reg);
199	}
200
201	void Write8(uint32 reg, uint8 value)
202	{
203		*(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
204	}
205
206	void Write16(uint32 reg, uint16 value)
207	{
208		*(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
209	}
210
211	void Write32(uint32 reg, uint32 value)
212	{
213		*(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
214	}
215};
216
217struct hda_widget {
218	uint32			node_id;
219
220	uint32			num_inputs;
221	int32			active_input;
222	uint32			inputs[MAX_INPUTS];
223	uint32			flags;
224
225	hda_widget_type	type;
226	uint32			pm;
227
228	struct {
229		uint32		audio;
230		uint32		output_amplifier;
231		uint32		input_amplifier;
232	} capabilities;
233
234	union {
235		struct {
236			uint32	formats;
237			uint32	rates;
238		} io;
239		struct {
240		} mixer;
241		struct {
242			uint32	capabilities;
243			uint32	config;
244		} pin;
245	} d;
246};
247
248struct hda_association {
249	uint32	index;
250	bool	enabled;
251	uint32 	pin_count;
252	uint32 	pins[MAX_ASSOCIATION_PINS];
253};
254
255#define WIDGET_FLAG_OUTPUT_PATH	0x01
256#define WIDGET_FLAG_INPUT_PATH	0x02
257#define WIDGET_FLAG_WIDGET_PATH	0x04
258
259/*!	This structure describes a single Audio Function Group. An AFG
260	is a group of audio widgets which can be used to configure multiple
261	streams of audio either from the HDA Link to an output device (= playback)
262	or from an input device to the HDA link (= recording).
263*/
264struct hda_audio_group {
265	hda_codec*		codec;
266	hda_widget		widget;
267
268	/* Multi Audio API data */
269	hda_stream*		playback_stream;
270	hda_stream*		record_stream;
271
272	uint32			widget_start;
273	uint32			widget_count;
274
275	uint32			association_count;
276	uint32			gpio;
277
278	hda_widget*		widgets;
279	hda_association		associations[MAX_ASSOCIATIONS];
280
281	hda_multi*		multi;
282};
283
284/*!	This structure describes a single codec module in the
285	HDA compliant device. This is a discrete component, which
286	can contain both Audio Function Groups, Modem Function Groups,
287	and other customized (vendor specific) Function Groups.
288
289	NOTE: ATM, only Audio Function Groups are supported.
290*/
291struct hda_codec {
292	uint16		vendor_id;
293	uint16		product_id;
294	uint32		subsystem_id;
295	uint8		major;
296	uint8		minor;
297	uint8		revision;
298	uint8		stepping;
299	uint8		addr;
300
301	uint32		quirks;
302
303	sem_id		response_sem;
304	uint32		responses[MAX_CODEC_RESPONSES];
305	uint32		response_count;
306
307	sem_id		unsol_response_sem;
308	thread_id	unsol_response_thread;
309	uint32		unsol_responses[MAX_CODEC_UNSOL_RESPONSES];
310	uint32		unsol_response_read, unsol_response_write;
311
312	hda_audio_group* audio_groups[HDA_MAX_AUDIO_GROUPS];
313	uint32		num_audio_groups;
314
315	struct hda_controller* controller;
316};
317
318
319#define MULTI_CONTROL_FIRSTID	1024
320#define MULTI_CONTROL_MASTERID	0
321#define MULTI_MAX_CONTROLS 128
322#define MULTI_MAX_CHANNELS 128
323
324struct hda_multi_mixer_control {
325	hda_multi	*multi;
326	int32 	nid;
327	int32 type;
328	bool input;
329	uint32 mute;
330	uint32 gain;
331	uint32 capabilities;
332	int32 index;
333	multi_mix_control	mix_control;
334};
335
336
337struct hda_multi {
338	hda_audio_group *group;
339	hda_multi_mixer_control controls[MULTI_MAX_CONTROLS];
340	uint32 control_count;
341
342	multi_channel_info chans[MULTI_MAX_CHANNELS];
343	uint32 output_channel_count;
344	uint32 input_channel_count;
345	uint32 output_bus_channel_count;
346	uint32 input_bus_channel_count;
347	uint32 aux_bus_channel_count;
348};
349
350
351/* driver.c */
352extern device_hooks gDriverHooks;
353extern pci_module_info* gPci;
354extern hda_controller gCards[MAX_CARDS];
355extern uint32 gNumCards;
356
357/* hda_codec.c */
358const char* get_widget_location(uint32 location);
359hda_widget* hda_audio_group_get_widget(hda_audio_group* audioGroup, uint32 nodeID);
360
361status_t hda_audio_group_get_widgets(hda_audio_group* audioGroup,
362	hda_stream* stream);
363hda_codec* hda_codec_new(hda_controller* controller, uint32 cad);
364void hda_codec_delete(hda_codec* codec);
365
366/* hda_multi_audio.c */
367status_t multi_audio_control(void* cookie, uint32 op, void* arg, size_t length);
368void get_settings_from_file();
369
370/* hda_controller.c: Basic controller support */
371status_t hda_hw_init(hda_controller* controller);
372void hda_hw_stop(hda_controller* controller);
373void hda_hw_uninit(hda_controller* controller);
374status_t hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses,
375	uint32 count);
376status_t hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload);
377status_t hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32 *response);
378
379/* hda_controller.c: Stream support */
380hda_stream* hda_stream_new(hda_audio_group* audioGroup, int type);
381void hda_stream_delete(hda_stream* stream);
382status_t hda_stream_setup_buffers(hda_audio_group* audioGroup,
383	hda_stream* stream, const char* desc);
384status_t hda_stream_start(hda_controller* controller, hda_stream* stream);
385status_t hda_stream_stop(hda_controller* controller, hda_stream* stream);
386
387#endif	/* _HDA_H_ */
388