1/*
2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef RADEON_HD_ACCELERANT_H
10#define RADEON_HD_ACCELERANT_H
11
12
13#include <ByteOrder.h>
14#include <edid.h>
15
16#include "atom.h"
17#include "dp.h"
18#include "encoder.h"
19#include "mode.h"
20#include "pll.h"
21#include "radeon_hd.h"
22#include "ringqueue.h"
23
24
25#define MAX_DISPLAY 2
26	// Maximum displays (more then two requires AtomBIOS)
27#define MAX_GPIO_PINS   64
28	// Maximum possible GPIO pins in gGPIOInfo
29
30struct gpu_state {
31	uint32 d1vgaControl;
32	uint32 d2vgaControl;
33	uint32 vgaRenderControl;
34	uint32 vgaHdpControl;
35	uint32 d1crtcControl;
36	uint32 d2crtcControl;
37};
38
39
40struct fb_info {
41	bool		valid;
42	uint64		vramStart;
43	uint64		vramEnd;
44	uint64		vramSize;
45
46	uint64		gartStart;
47	uint64		gartEnd;
48	uint64		gartSize;
49	uint64		agpBase;
50};
51
52
53struct accelerant_info {
54	vuint8*			regs;
55	area_id			regs_area;
56
57	radeon_shared_info* shared_info;
58	area_id			shared_info_area;
59
60	display_mode*	mode_list;		// cloned list of standard display modes
61	area_id			mode_list_area;
62
63	uint8*			rom;
64	area_id			rom_area;
65
66	edid1_info		edid_info;
67	bool			has_edid;
68
69	int				device;
70	bool			is_clone;
71
72	struct fb_info	fb;	// used for frame buffer info within MC
73
74	volatile uint32	dpms_mode;		// current driver dpms mode
75
76	uint32			maximumPixelClock;
77	uint32			displayClockFrequency;
78	uint32			dpExternalClock;
79
80	uint32			lvdsSpreadSpectrumID;
81
82	RingQueue*		ringQueue[RADEON_QUEUE_MAX]; // Ring buffer command processor
83};
84
85
86struct register_info {
87	uint16	crtcOffset;
88	uint16	vgaControl;
89	uint16	grphEnable;
90	uint16	grphControl;
91	uint16	grphSwapControl;
92	uint16	grphPrimarySurfaceAddr;
93	uint16	grphSecondarySurfaceAddr;
94	uint16	grphPrimarySurfaceAddrHigh;
95	uint16	grphSecondarySurfaceAddrHigh;
96	uint16	grphPitch;
97	uint16	grphSurfaceOffsetX;
98	uint16	grphSurfaceOffsetY;
99	uint16	grphXStart;
100	uint16	grphYStart;
101	uint16	grphXEnd;
102	uint16	grphYEnd;
103	uint16	modeDesktopHeight;
104	uint16	modeDataFormat;
105	uint16	viewportStart;
106	uint16	viewportSize;
107};
108
109
110typedef struct {
111	bool	valid;
112
113	uint32	hwPin;	// GPIO hardware pin on GPU
114	uint32	hwReg;	// GPIO register
115	uint32	hwMask;	// GPIO pin mask
116
117	struct {
118		bool valid;
119		bool hwCapable;	// can do hw assisted i2c
120		uint32 sclMaskReg;
121		uint32 sdaMaskReg;
122		uint32 sclMask;
123		uint32 sdaMask;
124
125		uint32 sclEnReg;
126		uint32 sdaEnReg;
127		uint32 sclEnMask;
128		uint32 sdaEnMask;
129
130		uint32 sclYReg;
131		uint32 sdaYReg;
132		uint32 sclYMask;
133		uint32 sdaYMask;
134
135		uint32 sclAReg;
136		uint32 sdaAReg;
137		uint32 sclAMask;
138		uint32 sdaAMask;
139	} i2c;
140} gpio_info;
141
142
143struct encoder_info {
144	bool		valid;
145	uint16		objectID;
146	uint32		type;
147	uint32		capabilities;
148	uint32		linkEnumeration; // ex. linkb == GRAPH_OBJECT_ENUM_ID2
149	bool		isExternal;
150	bool		isDPBridge;
151	struct pll_info	pll;
152};
153
154
155typedef struct {
156	uint32		objectID;
157	// i2c info
158	uint16		i2cPinIndex; // id of gpio pin for i2c router
159	uint32		i2cAddr;     // ?? hwPin??
160	// i2c pin mux
161	bool		ddcValid;
162	uint8		ddcMuxType;
163	uint8		ddcMuxControlPin;
164	uint8		ddcMuxState;
165	// clk / data pin mux
166	bool		cdValid;
167	uint8		cdMuxType;
168	uint8		cdMuxControlPin;
169	uint8		cdMuxState;
170} router_info;
171
172
173typedef struct {
174	bool		valid;
175	uint16		objectID;
176	uint32		type;
177	uint32		flags;
178	uint32		lvdsFlags;
179	uint16		i2cPinIndex; // id of gpio pin for i2c communications
180	uint16		hpdPinIndex; // id of gpio pin for hotplug detection
181	struct encoder_info encoder;
182	struct encoder_info encoderExternal;
183	dp_info		dpInfo;
184	router_info	router;
185} connector_info;
186
187
188typedef struct {
189	bool			attached;
190	bool			powered;
191	uint32			connectorIndex; // matches connector id in connector_info
192	register_info*	regs;
193	bool			foundRanges;
194	uint32			vfreqMax;
195	uint32			vfreqMin;
196	uint32			hfreqMax;
197	uint32			hfreqMin;
198	edid1_info		edidData;
199	display_mode	preferredMode;
200	display_mode	currentMode;
201} display_info;
202
203
204// register MMIO modes
205#define OUT 0x1	// Direct MMIO calls
206#define CRT 0x2	// Crt controller calls
207#define VGA 0x3 // Vga calls
208#define PLL 0x4 // PLL calls
209#define MC	0x5 // Memory controller calls
210
211
212extern accelerant_info* gInfo;
213extern atom_context* gAtomContext;
214extern display_info* gDisplay[MAX_DISPLAY];
215extern connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE];
216extern gpio_info* gGPIOInfo[MAX_GPIO_PINS];
217
218
219// register access
220
221inline uint32
222_read32(uint32 offset)
223{
224	return *(volatile uint32*)(gInfo->regs + offset);
225}
226
227
228inline void
229_write32(uint32 offset, uint32 value)
230{
231	*(volatile uint32 *)(gInfo->regs + offset) = value;
232}
233
234
235// AtomBIOS cail register calls (are *4... no clue why)
236inline uint32
237Read32Cail(uint32 offset)
238{
239	return _read32(offset * 4);
240}
241
242
243inline void
244Write32Cail(uint32 offset, uint32 value)
245{
246	_write32(offset * 4, value);
247}
248
249
250inline uint32
251Read32(uint32 subsystem, uint32 offset)
252{
253	switch (subsystem) {
254		default:
255		case OUT:
256		case VGA:
257		case CRT:
258		case PLL:
259			return _read32(offset);
260		case MC:
261			return _read32(offset);
262	};
263}
264
265
266inline void
267Write32(uint32 subsystem, uint32 offset, uint32 value)
268{
269	switch (subsystem) {
270		default:
271		case OUT:
272		case VGA:
273		case CRT:
274		case PLL:
275			_write32(offset, value);
276			return;
277		case MC:
278			_write32(offset, value);
279			return;
280	};
281}
282
283
284inline void
285Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask)
286{
287	uint32 temp;
288	switch (subsystem) {
289		default:
290		case OUT:
291		case VGA:
292		case MC:
293			temp = _read32(offset);
294			break;
295		case CRT:
296			temp = _read32(offset);
297			break;
298		case PLL:
299			temp = _read32(offset);
300			//temp = _read32PLL(offset);
301			break;
302	};
303
304	// only effect mask
305	temp &= ~mask;
306	temp |= value & mask;
307
308	switch (subsystem) {
309		default:
310		case OUT:
311		case VGA:
312		case MC:
313			_write32(offset, temp);
314			return;
315		case CRT:
316			_write32(offset, temp);
317			return;
318		case PLL:
319			_write32(offset, temp);
320			//_write32PLL(offset, temp);
321			return;
322	};
323}
324
325
326#endif	/* RADEON_HD_ACCELERANT_H */
327