/linux-master/arch/mips/mm/ |
H A D | uasm-mips.c | 51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, 53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, 54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, 55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 59 [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, 60 [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIM [all...] |
H A D | uasm-micromips.c | 43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD}, 44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, 45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD}, 46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, 47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 49 [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM}, 51 [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM}, 53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM}, 54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM}, 55 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS}, [all...] |
H A D | uasm.c | 17 RS = 0x001, enumerator in enum:fields
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/linux-master/certs/ |
H A D | check-blacklist-hashes.awk | 14 RS = ","
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/linux-master/drivers/macintosh/ |
H A D | via-macii.c | 40 #define RS 0x200 /* skip between registers */ macro 42 #define A RS /* A-side data */ 43 #define DIRB (2*RS) /* B-side direction (1=output) */ 44 #define DIRA (3*RS) /* A-side direction (1=output) */ 45 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 46 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 47 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 48 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 49 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ 50 #define T2CH (9*RS) /* Time [all...] |
H A D | via-cuda.c | 39 #define RS 0x200 /* skip between registers */ macro 41 #define A RS /* A-side data */ 42 #define DIRB (2*RS) /* B-side direction (1=output) */ 43 #define DIRA (3*RS) /* A-side direction (1=output) */ 44 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 45 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 46 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 47 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 48 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ 49 #define T2CH (9*RS) /* Time [all...] |
H A D | via-pmu.c | 83 #define RS 0x200 /* skip between registers */ macro 85 #define A RS /* A-side data */ 86 #define DIRB (2*RS) /* B-side direction (1=output) */ 87 #define DIRA (3*RS) /* A-side direction (1=output) */ 88 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 89 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 90 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 91 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 92 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ 93 #define T2CH (9*RS) /* Time [all...] |
/linux-master/arch/powerpc/platforms/powermac/ |
H A D | time.c | 52 #define RS 0x200 /* skip between registers */ macro 53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 54 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 57 #define ACR (11*RS) /* Auxiliary control register */ 58 #define IFR (13*RS) /* Interrupt flag register */
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/linux-master/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 546 the RS field in the instruction. This is used for extended 564 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 567 #define RS RC + 1 568 #define RT RS 570 #define RD RS 573 /* The RS and RT fields of the DS form stq and DQ form lq instructions, 575 #define RSQ RS + 1 579 /* The RS field of the tlbwe instruction, which is optional. */ 1786 the RS field in the instruction. This is used for extended 3265 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, R 565 #define RS macro [all...] |
/linux-master/tools/testing/selftests/powerpc/primitives/asm/ |
H A D | asm-compat.h | 23 #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
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H A D | ppc_asm.h | 470 #define MTOCRF(FXM, RS) \ 472 mtcrf (FXM), RS; \ 474 mtocrf (FXM), RS; \
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/linux-master/arch/powerpc/include/asm/ |
H A D | asm-compat.h | 23 #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
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H A D | ppc_asm.h | 470 #define MTOCRF(FXM, RS) \ 472 mtcrf (FXM), RS; \ 474 mtocrf (FXM), RS; \
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/linux-master/tools/testing/selftests/drivers/net/netdevsim/ |
H A D | ethtool-fec.sh | 56 check $? "$s" "$configured FEC encodings: RS LLRS 62 check $? "$s" "$configured FEC encodings: Auto Off RS 63 Active FEC encoding: RS" 83 $ETHTOOL --set-fec $NSIM_NETDEV encoding auto RS 88 "RS"' 90 check $? "$s" '"RS"' 105 $ETHTOOL --set-fec $NSIM_NETDEV encoding RS 2>/dev/null
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/linux-master/drivers/staging/fbtft/ |
H A D | fb_agm1264k-fl.c | 30 #define RS gpio.dc macro 192 gpiod_set_value(par->RS, 0); /* RS->0 (command mode) */ 354 gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */ 377 gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */
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/linux-master/drivers/edac/ |
H A D | pnd2_edac.c | 734 #define RS (BIT(7)) /* rank */ macro 763 R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), 773 R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), 783 R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), 793 R(10), C(7), C(8), C(9), R(11), RS, C(11), R(12), R(13), 803 R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), 813 R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), 823 R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), 833 R(9), R(10), C(8), C(9), R(11), RS, C(11), R(12), R(13), 843 R(8), R(9), R(10), C(9), R(11), RS, [all...] |
/linux-master/arch/m68k/fpsp040/ |
H A D | stan.S | 236 fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3)) 241 faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3)) 274 fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3)) 279 faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
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/linux-master/arch/mips/kernel/ |
H A D | traps.c | 716 #define RS BASE macro 731 int rs = (opcode & RS) >> 21;
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/linux-master/arch/m68k/ifpsp060/src/ |
H A D | fplsp.S | 5822 fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3)) 5826 fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3)) 5859 fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3)) 5863 fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3))
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