mips, uasm: Enable muhu opcode for MIPS R6

Enable the 'muhu' instruction, complementing the existing 'mulu', needed
to implement a MIPS32 BPF JIT.

Also fix a typo in the existing definition of 'dmulu'.

Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
Link: https://lore.kernel.org/bpf/20211005165408.2305108-2-johan.almbladh@anyfinetworks.com

MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR

CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

MIPS: uasm: Add div, mul and sel instructions for mipsr6

Add the following instructions for use by eBPF on mipsr6:
insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu,
insn_mulu, insn_seleqz, insn_selnez

Signed-off-by: Hassan Naveed <hnaveed@wavecomp.com>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: kafai@fb.com
Cc: songliubraving@fb.com
Cc: yhs@fb.com
Cc: netdev@vger.kernel.org
Cc: bpf@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: open list:MIPS <linux-mips@linux-mips.org>
Cc: open list <linux-kernel@vger.kernel.org>

mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X

Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.

Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Acked-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>

MIPS: Add some instructions to uasm.

Follow on patches for eBPF JIT require these additional instructions:

insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu,
insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav,
insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor,
insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu

... so, add them.

Sort the insn_* enumeration values alphabetically.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16367/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Optimize uasm insn lookup.

Instead of doing a linear search through the insn_table for each
instruction, use the opcode as direct index into the table. This will
give constant time lookup performance as the number of supported
opcodes increases. Make the tables const as they are only ever read.
For uasm-mips.c sort the table alphabetically, and remove duplicate
entries, uasm-micromips.c was already sorted and duplicate free.
There is a small savings in object size as struct insn loses a field:

$ size arch/mips/mm/uasm-mips.o arch/mips/mm/uasm-mips.o.save
text data bss dec hex filename
10040 0 0 10040 2738 arch/mips/mm/uasm-mips.o
9240 1120 0 10360 2878 arch/mips/mm/uasm-mips.o.save

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16365/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Remove needless ISA abstraction

We always either target MIPS32/MIPS64 or microMIPS, and always include
one & only one of uasm-mips.c or uasm-micromips.c. Therefore the
abstraction of the ISA in asm/uasm.h declaring functions for either ISA
is redundant & needless. Remove it to simplify the code.

This is largely the result of the following:

:%s/ISAOPC(\(.\{-}\))/uasm_i##\1/
:%s/ISAFUNC(\(.\{-}\))/\1/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/15844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add support for LHU.

The follow-on BPF JIT patches use the LHU instruction, so add it.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Steven J. Hill <steven.hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15743/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Handle low values in uasm_in_compat_space_p()

uasm_in_compat_space_p() determines whether the given value is in the
32-bit compatibility part of the 64-bit address space, i.e. is in 32-bit
sign-extended form, however it only handles the top half of the value
space (corresponding to the kernel compatibility segments in the upper
half of the address space). Since values < 2^31 (corresponding to the
low 2GiB of the address space) can also be handled using 32-bit
instructions (e.g. a LUI and ADDIU) rather than convoluted 64-bit
immediate generation, rewrite it with a cast to check whether the
address matches its 32-bit sign extended form.

This allows UASM_i_LA to be used to generate arbitrary 32-bit immediates
more efficiently on 64-bit CPUs, i.e. more like the li (load immediate)
pseudo-instruction.

For example this code to load the immediate (ST0_EXL | KSU_USER |
ST0_BEV | ST0_KX) into k0 with UASM_i_LA():

lui k0,0x0
dsll k0,k0,0x10
daddiu k0,k0,64
dsll k0,k0,0x10
daddiu k0,k0,146

Changes to this more efficient version:

lui k0,0x40
addiu k0,k0,146

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13778/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add MTHI/MTLO instructions

Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

MIPS: uasm: Add DI instruction

Add DI instruction for disabling interrupts to uasm so that KVM can use
uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

MIPS: uasm: Add CFCMSA/CTCMSA instructions

Add CFCMSA/CTCMSA instructions for accessing MSA control registers to
uasm so that KVM can use uasm for generating its entry point code at
runtime.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

MIPS: uasm: Add CFC1/CTC1 instructions

Add CFC1/CTC1 instructions for accessing FP control registers to uasm so
that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

MIPS: Loongson-3: Fast TLB refill handler

Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX

Make messages refer to all CN6XXX.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: mm: uasm: Add signed 9-bit immediate related macros

MIPS R6 redefines several instructions and reduces the immediate
field to 9-bits so add related macros for the microassembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

MIPS: Add MFHC0 and MTHC0 instructions to uasm.

New instructions for Extended Physical Addressing (XPA) functionality.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8453/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add SLT uasm instruction

It will be used later on by bpf-jit

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/7120/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add s3s1s2 instruction builder

It will be used later on by the SLT instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7119/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add lb uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

MIPS: uasm: Add mflo uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

MIPS: uasm: Add mul uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6736/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add lh uam instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6733/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add wsbh uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6732/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add sltu uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6731/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add sltiu uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6730/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add mfhi uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6728/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add divu uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6727/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add srlv uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6726/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add sllv uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Fixed conflict with
49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction].

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6725/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add u3u2u1 instruction builders

It will be used later on by the sllv and srlv instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6723/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: add MT ASE yield instruction

This patch allows use of the MT ASE yield instruction from uasm. It will
be used by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

MIPS: uasm: add wait instruction

This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

MIPS: uasm: add sync instruction

This patch allows use of the sync instruction from uasm. It will be used
by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

MIPS: uasm: add jalr instruction

This patch allows use of the jalr instruction from uasm. It will be used
by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

MIPS: uasm: add a label variant of beq

This patch allows for use of the beq instruction with labels from uasm,
much as bne & others already do. It will be used by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code

commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.

Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.

[1] https://lkml.org/lkml/2013/5/20/589

[ralf@linux-mips.org: Folded in Paul's followup fix.]

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: microMIPS: uasm: Split 'uasm.c' into two files.

Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the
functions specific to the classic MIPS ISA. The 'uasm.c' file
contains common code that can be used by classic or other ISAs
that could be supported by the kernel.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: kevink@paralogos.com
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/4922/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 0961103562ab958fa74f35043bf4f72e51ed6155)

MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add INS and EXT instructions.

These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

MIPS: Fixup ordering of micro assembler instructions.

A number of new instructions have been added to the micro assembler causing
the list to no longer be in alphabetical order. This patch fixes up the name
ordering.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3789/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Use WARN() in uasm for better diagnostics.

On the off chance that uasm ever warns about overflow, there is no way
to know what the offending instruction is.

Change the printks to WARNs, so we can get a nice stack trace. It has
the added benefit of being much more noticeable than the short single
line warning message, so is less likely to be ignored.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1905/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Add LDX and LWX instructions to uasm.

Needed by Octeon II optimized TLB handlers.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Pachwork: https://patchwork.linux-mips.org/patch/1903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Add DINSM to uasm.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Octeon: Apply CN63XXP1 errata workarounds.

The CN63XXP1 needs a couple of workarounds to ensure memory is not written
in unexpected ways.

All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We
pass a flag to the assembler to cover compiler generated code, and patch
uasm for the dynamically generated code.

The write buffer threshold is reduced to 4.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1672/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add option to export uasm API.

A 'select EXPORT_UASM' in Kconfig will cause the uasm to be exported
for use in modules. When it is exported, all the uasm data and code
cease to be __init and __initdata.

Also daddiu_bug cannot be __cpuinitdata if uasm is exported. The
cleanest thing is to just make it normal data.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: wim@iguana.be
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1500/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add BBIT0 and BBIT1 instructions

These are OCTEON specific instructions.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: wim@iguana.be
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1496/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add drotr32 and uasm_i_drotr_safe.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: wim@iguana.be
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1495/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: uasm: Add OR instruction.

This is needed for the fix of the M3 workaround.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Add SYSCALL to uasm.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/976/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Add TLBR and ROTR to uasm.

The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm. We also add a UASM_i_ROTR macro.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h

Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
To: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Add drotr and dins instructions to uasm.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] Make two functions static

The following routines

uasm_rel_highest()
uasm_rel_higher()

are needlessly defined global. This patch makes them static.

Compile-tested using a customized config for the Malta board. Booting
the same board up to the shell prompt was also successful with this
patch applied.

Spotted by sparse.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] Reimplement clear_page/copy_page

Fold the SB-1 specific implementation of clear_page/copy_page in the
generic version, and rewrite that one in tlbex style. The immediate
benefits:
- It converts the compile-time workaround for SB-1 pass 1 prefetches
to a more efficient run-time check.
- It allows adjustment of loop unfolling, which helps to reduce the
number of redundant cdex cache ops.
- It fixes some esoteric cornercases (the cache line length calculations
can go wrong, and support for 64k pages without prefetch instructions
will overflow the addiu immediate).
- Somewhat better guesses of "good" prefetch values.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] Fix loads of section missmatches

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] Split the micro-assembler from tlbex.c.

This patch moves the micro-assembler in a separate implementation, as
it is useful for further run-time optimizations. The only change in
behaviour is cutting down printk noise at kernel startup time.

Checkpatch complains about macro parameters which aren't protected by
parentheses. I believe this is a flaw in checkpatch, the paste operator
used in those macros won't work with parenthesised parameters.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>