/linux-master/drivers/media/radio/wl128x/ |
H A D | fmdrv_tx.c | 26 ret = fmc_send_cmd(fmdev, MONO_SET, REG_WR, &payload, 41 ret = fmc_send_cmd(fmdev, RDS_DATA_SET, REG_WR, rds_text, 48 ret = fmc_send_cmd(fmdev, DISPLAY_MODE, REG_WR, &payload, 63 ret = fmc_send_cmd(fmdev, PI_SET, REG_WR, &payload, 70 ret = fmc_send_cmd(fmdev, DI_SET, REG_WR, &payload, 86 ret = fmc_send_cmd(fmdev, RDS_CONFIG_DATA_SET, REG_WR, &payload, 121 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, 158 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, 178 ret = fmc_send_cmd(fmdev, TA_SET, REG_WR, &payload, 198 ret = fmc_send_cmd(fmdev, TX_BAND_SET, REG_WR, [all...] |
H A D | fmdrv_rx.c | 49 ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload, 56 ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload, 64 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, 78 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, 85 ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, 120 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, 146 ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload, 201 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, 208 ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload, 222 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, [all...] |
H A D | fmdrv_common.c | 877 if (!fm_send_cmd(fmdev, RDS_PI_SET, REG_WR, &payload, sizeof(payload), NULL)) 896 if (!fm_send_cmd(fmdev, RDS_PI_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) 915 if (!fm_send_cmd(fmdev, AF_FREQ_SET, REG_WR, &payload, sizeof(payload), NULL)) 930 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) 944 if (!fm_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, 1025 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, 1221 ret = fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload, 1330 if (fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload,
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H A D | fmdrv_common.h | 16 #define REG_WR 0x0 macro
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/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_init_ops.h | 57 REG_WR(bp, addr + i*4, data[i]); 265 REG_WR(bp, addr, op->write.val); 497 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); 498 REG_WR(bp, read_arb_addr[i].add, 500 REG_WR(bp, read_arb_addr[i].ubound, 508 REG_WR(bp, write_arb_addr[i].l, 511 REG_WR(bp, write_arb_addr[i].add, 514 REG_WR(bp, write_arb_addr[i].ubound, 519 REG_WR(bp, write_arb_addr[i].l, 523 REG_WR(b [all...] |
H A D | bnx2x_main.c | 317 REG_WR(bp, addr, U64_LO(mapping)); 318 REG_WR(bp, addr + 4, U64_HI(mapping)); 477 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 479 REG_WR(bp, dmae_reg_go_c[idx], 1); 869 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 884 REG_WR(bp, addr, val); 899 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1420 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1430 REG_WR(bp, comp_addr, 0); 1527 REG_WR(b [all...] |
H A D | bnx2x_init.h | 233 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos); 238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); 243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); 255 REG_WR(bp, reg_addr, reg_bit_map); 575 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */ 577 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */ 579 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */ 580 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */ 581 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */ 688 REG_WR(b [all...] |
H A D | bnx2x_link.c | 225 REG_WR(bp, reg, val); 234 REG_WR(bp, reg, val); 262 REG_WR(bp, params->lfa_base + 381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 469 REG_WR(b [all...] |
H A D | bnx2x_sriov.c | 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 107 REG_WR(bp, igu_addr_ctl, ctl); 681 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 687 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 688 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 689 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 690 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 712 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 723 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 724 REG_WR(b [all...] |
H A D | bnx2x_cmn.h | 650 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 670 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 942 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD); 943 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD); 944 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD); 1224 REG_WR(bp, addr + (i * 4), data[i]); 1335 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
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H A D | bnx2x_ethtool.c | 871 REG_WR(bp, write_addr[j], page_addr[i]); 1266 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1299 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1328 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1340 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1355 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1358 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1362 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1628 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1631 REG_WR(b [all...] |
H A D | bnx2x.h | 181 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) macro 213 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 218 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 225 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 234 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
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H A D | bnx2x_cmn.c | 1494 REG_WR(bp, BAR_USTRORM_INTMEM + 1497 REG_WR(bp, BAR_USTRORM_INTMEM + 2580 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1); 2610 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
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H A D | bnx2x_dcb.c | 54 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */ 68 REG_WR(bp, addr + i, *buff);
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H A D | bnx2x_sp.c | 829 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 3569 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]);
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/linux-master/drivers/net/ethernet/qlogic/qed/ |
H A D | qed_hw.c | 176 REG_WR(p_hwfn, 223 REG_WR(p_hwfn, bar_addr, val); 316 REG_WR(p_hwfn, 333 REG_WR(p_hwfn, 349 REG_WR(p_hwfn, 369 REG_WR(p_hwfn,
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H A D | qed_vf.c | 89 REG_WR(p_hwfn, 93 REG_WR(p_hwfn, 102 REG_WR(p_hwfn, (uintptr_t)&zone_data->trigger, *((u32 *)&trigger));
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H A D | qed_init_ops.c | 619 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
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H A D | qed.h | 962 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) macro
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H A D | qed_dev.c | 2495 REG_WR(p_hwfn, addr, 0); 2515 REG_WR(p_hwfn, addr, 0);
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H A D | qed_sriov.c | 1224 REG_WR(p_hwfn, 3721 REG_WR(p_hwfn,
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/linux-master/drivers/scsi/bnx2i/ |
H A D | bnx2i.h | 130 #define REG_WR(__hba, offset, val) \ macro
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