Lines Matching refs:REG_WR
233 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
255 REG_WR(bp, reg_addr, reg_bit_map);
575 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
577 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
579 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
580 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
581 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
688 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
712 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
735 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
736 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
737 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
738 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
766 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
777 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,