Searched refs:REG_SET (Results 1 - 25 of 92) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c78 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
80 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
83 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
85 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
92 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
95 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
H A Ddcn20_mpc.c66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
293 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
388 REG_SET(MPCC_OGAM_LUT_DAT
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H A Ddcn20_hubp.c67 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
70 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
73 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
93 REG_SET(BLANK_OFFSET_1, 0,
96 REG_SET(DST_DIMENSIONS, 0,
103 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
107 REG_SET(VBLANK_PARAMETERS_1, 0,
111 REG_SET(NOM_PARAMETERS_0, 0,
115 REG_SET(NOM_PARAMETERS_1, 0,
118 REG_SET(NOM_PARAMETERS_
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H A Ddcn20_dpp_cm.c99 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
101 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
102 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
103 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
105 REG_SET(CM_DGAM_LUT_DATA, 0,
107 REG_SET(CM_DGAM_LUT_DATA, 0,
109 REG_SET(CM_DGAM_LUT_DATA, 0,
170 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
207 REG_SET(
307 REG_SET(CM_ICSC_CONTRO
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c57 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
60 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
116 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
145 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRES
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H A Ddcn30_dpp_cm.c94 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
96 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
102 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
104 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
106 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
111 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg);
113 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green);
115 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
120 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg);
122 REG_SET(CM_GAMCOR_LUT_DAT
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H A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg);
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green);
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
228 REG_SET(DWB_OGAM_LUT_DAT
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/linux-master/arch/arm/mach-imx/
H A Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR;
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
229 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
233 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
236 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
254 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
320 REG_SET(MPCC_BOT_SE
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H A Ddcn10_hubp.c396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_
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H A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
154 REG_SET(
269 REG_SET(CM_TEST_DEBUG_INDEX, 0,
303 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
391 REG_SET(CM_MEM_PWR_CTRL, 0,
406 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
407 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
408 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
410 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
411 REG_SET(CM_RGAM_LUT_DAT
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
130 REG_SET(CUR_SURFACE_ADDRESS, 0,
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
193 REG_SET(DC_LUT_RW_INDEX, 0,
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
H A Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
344 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
347 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
367 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
370 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
445 REG_SET(SCL_VERT_FILTER_CONTROL, 0,
460 REG_SET(SCL_HORZ_FILTER_CONTRO
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c142 REG_SET(OPTC_BYTES_PER_PIXEL, 0,
183 REG_SET(OPTC_MEMORY_CONFIG, 0,
199 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
214 REG_SET(OPTC_MEMORY_CONFIG, 0,
225 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
293 REG_SET(OTG_GLOBAL_CONTROL0, 0,
303 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
331 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
353 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
377 REG_SET(OTG_MASTER_UPDATE_LOC
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubbub.c189 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
203 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
213 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
223 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
233 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
247 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
257 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
267 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
277 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
291 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_
[all...]
H A Ddcn31_hpo_dp_link_encoder.c213 REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom);
215 REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom);
217 REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom);
219 REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom);
221 REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom);
223 REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom);
225 REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom);
227 REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom);
229 REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom);
231 REG_SET(DP_DPHY_SYM32_TP_CUSTOM
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c51 REG_SET(OTG_GLOBAL_CONTROL0, 0,
53 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
67 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
69 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubbub.c184 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
198 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
208 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
218 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
228 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
242 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
252 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
262 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
272 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
286 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_
[all...]
H A Ddcn32_mpc.c74 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);
87 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
136 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
238 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
239 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
241 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
244 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
245 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
247 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
250 REG_SET(MPCC_MCM_1DLUT_LUT_DAT
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c99 REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);
118 REG_SET(gpio.MASK_reg, regval,
127 REG_SET(gpio.MASK_reg, regval,
163 REG_SET(gpio.MASK_reg, regval,
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c52 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
125 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
174 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
213 REG_SET(OPTC_MEMORY_CONFIG, 0,
227 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
252 REG_SET(OPTC_MEMORY_CONFIG, 0,
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c82 REG_SET(OTG_VSTARTUP_PARAM, 0,
89 REG_SET(OTG_VREADY_PARAM, 0,
97 REG_SET(OTG_STEREO_CONTROL, 0,
123 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
133 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
187 REG_SET(OTG_H_TOTAL, 0,
218 REG_SET(OTG_V_TOTAL, 0,
670 REG_SET(OTG_GLOBAL_CONTROL0, 0,
672 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
686 REG_SET(OTG_MASTER_UPDATE_LOC
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c70 REG_SET(OPTC_MEMORY_CONFIG, 0,
90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
178 REG_SET(OTG_V_TOTAL_MID, 0,
227 REG_SET(OTG_H_TIMING_CNTL, 0,
230 REG_SET(OPTC_MEMORY_CONFIG, 0,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c95 REG_SET(VBLANK_PARAMETERS_5, 0,
103 REG_SET(VBLANK_PARAMETERS_6, 0,
111 REG_SET(FLIP_PARAMETERS_3, 0,
119 REG_SET(FLIP_PARAMETERS_4, 0,
122 REG_SET(FLIP_PARAMETERS_5, 0,
125 REG_SET(FLIP_PARAMETERS_6, 0,
242 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
245 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
618 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
622 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_
[all...]
H A Ddcn21_hubbub.c113 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
115 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
117 REG_SET(DCN_VM_FB_OFFSET, 0,
119 REG_SET(DCN_VM_AGP_BOT, 0,
121 REG_SET(DCN_VM_AGP_TOP, 0,
123 REG_SET(DCN_VM_AGP_BASE, 0,
172 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
182 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
192 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
217 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_
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