/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument 29 if (RC == &NVPTX::Float32RegsRegClass) 31 if (RC == &NVPTX::Float16RegsRegClass) 37 if (RC == &NVPTX::Float16x2RegsRegClass) 39 if (RC == &NVPTX::Float64RegsRegClass) 41 if (RC == &NVPTX::Int64RegsRegClass) 61 if (RC == &NVPTX::Int32RegsRegClass) 63 if (RC == &NVPTX::Int16RegsRegClass) 65 if (RC == &NVPTX::Int1RegsRegClass) 67 if (RC 72 getNVPTXRegClassStr(TargetRegisterClass const *RC) argument [all...] |
H A D | NVPTXRegisterInfo.h | 59 std::string getNVPTXRegClassName(const TargetRegisterClass *RC); 60 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 69 // Compute all information about RC. 70 void compute(const TargetRegisterClass *RC) const; 72 // Return an up-to-date RCInfo for RC. 73 const RCInfo &get(const TargetRegisterClass *RC) const { 74 const RCInfo &RCI = RegClass[RC->getID()]; 76 compute(RC); 88 /// registers in RC in the current function. 89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 90 return get(RC).NumRegs; 93 /// getOrder - Returns the preferred allocation order for RC 122 getMinCost(const TargetRegisterClass *RC) argument 130 getLastCostChange(const TargetRegisterClass *RC) argument [all...] |
H A D | TargetRegisterInfo.h | 118 bool hasSubClass(const TargetRegisterClass *RC) const { 119 return RC != this && hasSubClassEq(RC); 122 /// Returns true if RC is a sub-class of or equal to this class. 123 bool hasSubClassEq(const TargetRegisterClass *RC) const { 124 unsigned ID = RC->getID(); 130 bool hasSuperClass(const TargetRegisterClass *RC) const { 131 return RC->hasSubClass(this); 134 /// Returns true if RC is a super-class of or equal to this class. 135 bool hasSuperClassEq(const TargetRegisterClass *RC) cons 288 isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const argument [all...] |
H A D | ExecutionDomainFix.h | 111 const TargetRegisterClass *const RC; 130 ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC) 131 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local 43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); 45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 46 TRI.getSpillAlignment(RC), true); 56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local 59 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 60 TRI.getSpillAlignment(RC), true); 69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local 72 unsigned Size = TRI.getSpillSize(RC); 73 unsigned Align = TRI.getSpillAlignment(RC); [all...] |
/freebsd-11-stable/contrib/ofed/libibverbs/ |
H A D | opcode.h | 82 /* RC */ 83 IBV_OPCODE(RC, SEND_FIRST), 84 IBV_OPCODE(RC, SEND_MIDDLE), 85 IBV_OPCODE(RC, SEND_LAST), 86 IBV_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE), 87 IBV_OPCODE(RC, SEND_ONLY), 88 IBV_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE), 89 IBV_OPCODE(RC, RDMA_WRITE_FIRST), 90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE), 91 IBV_OPCODE(RC, RDMA_WRITE_LAS [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | RegisterBankEmitter.cpp | 72 void addRegisterClass(const CodeGenRegisterClass *RC) { argument 74 [&RC](const CodeGenRegisterClass *X) { 75 return X == RC; 86 RCWithLargestRegsSize = RC; 88 RC->RSI.get(DefaultMode).SpillSize) 89 RCWithLargestRegsSize = RC; 90 assert(RCWithLargestRegsSize && "RC was nullptr?"); 92 RCs.emplace_back(RC); 164 /// \param RC The register class to search. 165 /// \param Kind A debug string containing the path the visitor took to reach RC 169 visitRegisterBankClasses( CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC, const Twine Kind, std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn, SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) argument 245 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); local [all...] |
H A D | RegisterInfoEmitter.cpp | 146 for (const auto &RC : RegisterClasses) 147 OS << " " << RC.getName() << "RegClassID" 148 << " = " << RC.EnumValue << ",\n"; 201 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 203 for (const auto &RC : RegBank.getRegClasses()) { 204 const CodeGenRegister::Vec &Regs = RC.getMembers(); 205 if (Regs.empty() || RC.Artificial) 209 RC.buildRegUnitSet(RegBank, RegUnits); 213 OS << "}, \t// " << RC.getName() << "\n"; 216 << " return RCWeightTable[RC [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyExplicitLocals.cpp | 83 static unsigned getDropOpcode(const TargetRegisterClass *RC) { argument 84 if (RC == &WebAssembly::I32RegClass) 86 if (RC == &WebAssembly::I64RegClass) 88 if (RC == &WebAssembly::F32RegClass) 90 if (RC == &WebAssembly::F64RegClass) 92 if (RC == &WebAssembly::V128RegClass) 94 if (RC == &WebAssembly::EXNREFRegClass) 100 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { argument 101 if (RC == &WebAssembly::I32RegClass) 103 if (RC 117 getLocalSetOpcode(const TargetRegisterClass *RC) argument 134 getLocalTeeOpcode(const TargetRegisterClass *RC) argument 151 typeForRegClass(const TargetRegisterClass *RC) argument 243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local 278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local 353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 87 /// compute - Compute the preferred allocation order for RC with reserved 90 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 91 assert(RC && "no register class given"); 92 RCInfo &RCI = RegClass[RC->getID()]; 96 unsigned NumRegs = RC->getNumRegs(); 109 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 146 // Check if RC is a proper sub-class. 148 TRI->getLargestLegalSuperClass(RC, *MF)) 149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 156 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") 170 const TargetRegisterClass *RC = nullptr; local [all...] |
H A D | LiveStacks.cpp | 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 66 S2RCMap.insert(std::make_pair(Slot, RC)); 70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 83 if (RC) 84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
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H A D | TargetRegisterInfo.cpp | 173 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 174 if (!RC || RC->isAllocatable()) 175 return RC; 177 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); 197 for (const TargetRegisterClass* RC : regclasses()) { 198 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) && 199 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) 200 BestRC = RC; [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBank.cpp | 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local 36 if (!covers(RC)) 42 // RegisterBankInfo to find the subclasses of RC, to make sure 47 if (!RC.hasSubClassEq(&SubRC)) 60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { 62 return ContainedRegClasses.test(RC.getID()); 104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local 106 if (!covers(RC)) 111 OS << TRI->getRegClassName(&RC);
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/freebsd-11-stable/sys/ofed/include/rdma/ |
H A D | ib_pack.h | 114 /* RC */ 115 IB_OPCODE(RC, SEND_FIRST), 116 IB_OPCODE(RC, SEND_MIDDLE), 117 IB_OPCODE(RC, SEND_LAST), 118 IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE), 119 IB_OPCODE(RC, SEND_ONLY), 120 IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE), 121 IB_OPCODE(RC, RDMA_WRITE_FIRST), 122 IB_OPCODE(RC, RDMA_WRITE_MIDDLE), 123 IB_OPCODE(RC, RDMA_WRITE_LAS [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.h | 129 bool isSGPRClass(const TargetRegisterClass *RC) const { 130 return !hasVGPRs(RC) && !hasAGPRs(RC); 139 const TargetRegisterClass *RC; local 141 RC = MRI.getRegClass(Reg); 143 RC = getPhysRegClass(Reg); 144 return isSGPRClass(RC); 148 bool isAGPRClass(const TargetRegisterClass *RC) const { 149 return hasAGPRs(RC) && !hasVGPRs(RC); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); local 93 unsigned ID = RC.getID(); 96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); 108 << TRI.getRegClassName(&RC) << '\n'; 119 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass, 121 if (RC.contains(Reg)) 122 return TRI.getRegSizeInBits(RC); 125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) 126 return TRI.getRegSizeInBits(*RC); 133 const TargetRegisterClass &RC, unsigne 132 composeWithSubRegIndex( const TargetRegisterClass &RC, unsigned Idx) const argument [all...] |
H A D | BitTracker.h | 54 void put(RegisterRef RR, const RegisterCell &RC); 315 bool meet(const RegisterCell &RC, unsigned SelfR); 316 RegisterCell &insert(const RegisterCell &RC, const BitMask &M); 320 RegisterCell &cat(const RegisterCell &RC); // Concatenate. 324 bool operator== (const RegisterCell &RC) const; 325 bool operator!= (const RegisterCell &RC) const { 326 return !operator==(RC); 348 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC); 364 RegisterCell RC(Width); 366 RC [all...] |
/freebsd-11-stable/contrib/ntp/scripts/build/ |
H A D | VersionName | 59 rc::dev|RC::dev) 60 NAME="${NAME}-RC" 62 rc::stable|RC::stable) 63 NAME="${NAME}-RC${rcpoint}"
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMRegisterBankInfo.h | 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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H A D | Thumb1InstrInfo.h | 46 const TargetRegisterClass *RC, 52 const TargetRegisterClass *RC,
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/freebsd-11-stable/crypto/openssl/util/ |
H A D | domd | 25 RC=$? 36 RC=$? 48 exit $RC
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 72 const TargetRegisterClass *RC; local 75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 77 V0 = RegInfo.createVirtualRegister(RC); 78 V1 = RegInfo.createVirtualRegister(RC); 153 const TargetRegisterClass &RC = local 158 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), 159 TRI.getSpillAlignment(RC), false); 168 const TargetRegisterClass &RC = Mips::GPR32RegClass; local 173 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), fals 192 getMoveF64ViaSpillFI(const TargetRegisterClass *RC) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | CGSCCPassManager.cpp | 165 for (auto &RC : G->postorder_ref_sccs()) 166 for (auto &C : RC) { 436 RefSCC *RC = &InitialRC; local 511 if (&TargetRC == RC && E.isCall()) { 514 RC->switchTrivialInternalEdgeToRef(N, E.getNode()); 517 C = incorporateNewSCCRange(RC->switchInternalEdgeToRef(N, E.getNode()), 534 if (&TargetRC == RC) 537 RC->removeOutgoingEdge(N, *TargetN); 545 auto NewRefSCCs = RC->removeInternalRefEdge(N, DeadTargets); 548 UR.InvalidatedRefSCCs.insert(RC); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.h | 70 getSubClassWithSubReg(const TargetRegisterClass *RC, 74 getLargestLegalSuperClass(const TargetRegisterClass *RC, 92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 99 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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