1327122Sdim//===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===// 2327122Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6327122Sdim// 7327122Sdim//===----------------------------------------------------------------------===// 8327122Sdim// 9327122Sdim// This file implements the live stack slot analysis pass. It is analogous to 10327122Sdim// live interval analysis except it's analyzing liveness of stack slots rather 11327122Sdim// than registers. 12327122Sdim// 13327122Sdim//===----------------------------------------------------------------------===// 14327122Sdim 15327122Sdim#include "llvm/CodeGen/LiveStacks.h" 16327122Sdim#include "llvm/CodeGen/LiveIntervals.h" 17327122Sdim#include "llvm/CodeGen/Passes.h" 18327122Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 19327122Sdim#include "llvm/CodeGen/TargetSubtargetInfo.h" 20327122Sdim#include "llvm/Support/Debug.h" 21327122Sdim#include "llvm/Support/raw_ostream.h" 22327122Sdimusing namespace llvm; 23327122Sdim 24327122Sdim#define DEBUG_TYPE "livestacks" 25327122Sdim 26327122Sdimchar LiveStacks::ID = 0; 27327122SdimINITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE, 28327122Sdim "Live Stack Slot Analysis", false, false) 29327122SdimINITIALIZE_PASS_DEPENDENCY(SlotIndexes) 30327122SdimINITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE, 31327122Sdim "Live Stack Slot Analysis", false, false) 32327122Sdim 33327122Sdimchar &llvm::LiveStacksID = LiveStacks::ID; 34327122Sdim 35327122Sdimvoid LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { 36327122Sdim AU.setPreservesAll(); 37327122Sdim AU.addPreserved<SlotIndexes>(); 38327122Sdim AU.addRequiredTransitive<SlotIndexes>(); 39327122Sdim MachineFunctionPass::getAnalysisUsage(AU); 40327122Sdim} 41327122Sdim 42327122Sdimvoid LiveStacks::releaseMemory() { 43327122Sdim // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd. 44327122Sdim VNInfoAllocator.Reset(); 45327122Sdim S2IMap.clear(); 46327122Sdim S2RCMap.clear(); 47327122Sdim} 48327122Sdim 49327122Sdimbool LiveStacks::runOnMachineFunction(MachineFunction &MF) { 50327122Sdim TRI = MF.getSubtarget().getRegisterInfo(); 51327122Sdim // FIXME: No analysis is being done right now. We are relying on the 52327122Sdim // register allocators to provide the information. 53327122Sdim return false; 54327122Sdim} 55327122Sdim 56327122SdimLiveInterval & 57327122SdimLiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { 58327122Sdim assert(Slot >= 0 && "Spill slot indice must be >= 0"); 59327122Sdim SS2IntervalMap::iterator I = S2IMap.find(Slot); 60327122Sdim if (I == S2IMap.end()) { 61360784Sdim I = S2IMap 62360784Sdim .emplace( 63360784Sdim std::piecewise_construct, std::forward_as_tuple(Slot), 64360784Sdim std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F)) 65327122Sdim .first; 66327122Sdim S2RCMap.insert(std::make_pair(Slot, RC)); 67327122Sdim } else { 68327122Sdim // Use the largest common subclass register class. 69327122Sdim const TargetRegisterClass *OldRC = S2RCMap[Slot]; 70327122Sdim S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 71327122Sdim } 72327122Sdim return I->second; 73327122Sdim} 74327122Sdim 75327122Sdim/// print - Implement the dump method. 76327122Sdimvoid LiveStacks::print(raw_ostream &OS, const Module*) const { 77327122Sdim 78327122Sdim OS << "********** INTERVALS **********\n"; 79327122Sdim for (const_iterator I = begin(), E = end(); I != E; ++I) { 80327122Sdim I->second.print(OS); 81327122Sdim int Slot = I->first; 82327122Sdim const TargetRegisterClass *RC = getIntervalRegClass(Slot); 83327122Sdim if (RC) 84327122Sdim OS << " [" << TRI->getRegClassName(RC) << "]\n"; 85327122Sdim else 86327122Sdim OS << " [Unknown]\n"; 87327122Sdim } 88327122Sdim} 89