Searched refs:POSTING_READ (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_hdmi.c171 POSTING_READ(VIDEO_DIP_CTL);
209 POSTING_READ(reg);
250 POSTING_READ(reg);
288 POSTING_READ(reg);
321 POSTING_READ(ctl_reg);
392 POSTING_READ(reg);
412 POSTING_READ(reg);
422 POSTING_READ(reg);
448 POSTING_READ(reg);
471 POSTING_READ(re
[all...]
H A Dintel_ddi.c188 POSTING_READ(_FDI_RXA_CTL);
216 POSTING_READ(DDI_BUF_CTL(PORT_E));
226 POSTING_READ(_FDI_RXA_CTL);
235 POSTING_READ(_FDI_RXA_MISC);
257 POSTING_READ(DDI_BUF_CTL(PORT_E));
264 POSTING_READ(DP_TP_CTL(PORT_E));
270 POSTING_READ(_FDI_RXA_CTL);
277 POSTING_READ(_FDI_RXA_MISC);
774 POSTING_READ(SPLL_CTL);
784 POSTING_READ(WRPLL_CTL
[all...]
H A Di915_irq.c50 POSTING_READ(DEIMR);
60 POSTING_READ(DEIMR);
73 POSTING_READ(reg);
85 POSTING_READ(reg);
426 POSTING_READ(GEN7_MISCCPCTL);
435 POSTING_READ(GEN7_L3CDERRST1);
523 POSTING_READ(GEN6_PMIMR);
735 POSTING_READ(DEIER);
762 POSTING_READ(DEIER);
822 POSTING_READ(DEIE
[all...]
H A Dintel_sprite.c147 POSTING_READ(SPRSURF(pipe));
164 POSTING_READ(SPRSURF(pipe));
194 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
307 POSTING_READ(DVSSURF(pipe));
323 POSTING_READ(DVSSURF(pipe));
384 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
H A Dintel_dp.c1040 POSTING_READ(PCH_PP_CONTROL);
1063 POSTING_READ(PCH_PP_CONTROL);
1133 POSTING_READ(PCH_PP_CONTROL);
1141 POSTING_READ(PCH_PP_CONTROL);
1148 POSTING_READ(PCH_PP_CONTROL);
1170 POSTING_READ(PCH_PP_CONTROL);
1199 POSTING_READ(PCH_PP_CONTROL);
1219 POSTING_READ(PCH_PP_CONTROL);
1245 POSTING_READ(DP_A);
1270 POSTING_READ(DP_
[all...]
H A Dintel_display.c462 POSTING_READ(DPIO_CTL);
464 POSTING_READ(DPIO_CTL);
1461 POSTING_READ(reg);
1464 POSTING_READ(reg);
1467 POSTING_READ(reg);
1496 POSTING_READ(reg);
1606 POSTING_READ(reg);
1650 POSTING_READ(reg);
2127 POSTING_READ(reg);
2218 POSTING_READ(re
[all...]
H A Di915_suspend.c468 POSTING_READ(dpll_a_reg);
475 POSTING_READ(dpll_a_reg);
479 POSTING_READ(_DPLL_A_MD);
537 POSTING_READ(dpll_b_reg);
544 POSTING_READ(dpll_b_reg);
548 POSTING_READ(_DPLL_B_MD);
802 POSTING_READ(VGA_PD);
H A Dintel_crt.c278 POSTING_READ(PCH_ADPA);
504 POSTING_READ(pipeconf_reg);
667 POSTING_READ(PCH_ADPA);
H A Dintel_ringbuffer.c759 POSTING_READ(GTIMR);
776 POSTING_READ(GTIMR);
794 POSTING_READ(IMR);
811 POSTING_READ(IMR);
879 POSTING_READ(mmio);
940 POSTING_READ(GTIMR);
961 POSTING_READ(GTIMR);
1491 POSTING_READ(RING_TAIL(ring->mmio_base));
H A Di915_drv.c690 POSTING_READ(D_STATE);
697 POSTING_READ(DEBUG_RESET_I830);
701 POSTING_READ(DEBUG_RESET_I830);
707 POSTING_READ(D_STATE);
H A Dintel_pm.c195 POSTING_READ(GEN6_BLITTER_ECOSKPD);
2379 POSTING_READ(VIDSTART);
2476 POSTING_READ(GEN6_RPNSWREQ);
2752 POSTING_READ(PWRCTXA);
2755 POSTING_READ(RSTDBYCTL);
3386 POSTING_READ(ECR);
4271 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4288 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4301 POSTING_READ(ECOBUS);
4319 POSTING_READ(ECOBU
[all...]
H A Dintel_panel.c351 POSTING_READ(reg);
H A Dintel_lvds.c135 POSTING_READ(lvds_reg);
171 POSTING_READ(lvds_reg);
H A Dintel_iic.c177 POSTING_READ(bus->gpio_reg);
195 POSTING_READ(bus->gpio_reg);
H A Di915_gem.c2815 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2838 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2882 POSTING_READ(reg);
2914 POSTING_READ(FENCE_REG_830_0 + reg * 4);
4176 POSTING_READ(GEN7_MISCCPCTL);
4189 POSTING_READ(GEN7_L3LOG_BASE);
H A Dintel_tv.c1222 POSTING_READ(TV_DAC);
1252 POSTING_READ(TV_CTL);
H A Di915_gem_gtt.c481 POSTING_READ(GFX_FLSH_CNTL_GEN6);
H A Dintel_sdvo.c1252 POSTING_READ(intel_sdvo->sdvo_reg);
1256 POSTING_READ(intel_sdvo->sdvo_reg);
H A Di915_drv.h1749 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) macro

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