1235783Skib/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2235783Skib */ 3235783Skib/* 4235783Skib * 5235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6235783Skib * All Rights Reserved. 7235783Skib * 8235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 9235783Skib * copy of this software and associated documentation files (the 10235783Skib * "Software"), to deal in the Software without restriction, including 11235783Skib * without limitation the rights to use, copy, modify, merge, publish, 12235783Skib * distribute, sub license, and/or sell copies of the Software, and to 13235783Skib * permit persons to whom the Software is furnished to do so, subject to 14235783Skib * the following conditions: 15235783Skib * 16235783Skib * The above copyright notice and this permission notice (including the 17235783Skib * next paragraph) shall be included in all copies or substantial portions 18235783Skib * of the Software. 19235783Skib * 20235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27235783Skib * 28235783Skib */ 29235783Skib 30235783Skib#include <sys/cdefs.h> 31235783Skib__FBSDID("$FreeBSD$"); 32235783Skib 33235783Skib#ifndef _I915_DRV_H_ 34235783Skib#define _I915_DRV_H_ 35235783Skib 36235783Skib#include <dev/agp/agp_i810.h> 37235783Skib#include <dev/drm2/drm_mm.h> 38235783Skib#include <dev/drm2/i915/i915_reg.h> 39235783Skib#include <dev/drm2/i915/intel_ringbuffer.h> 40235783Skib#include <dev/drm2/i915/intel_bios.h> 41235783Skib 42235783Skib/* General customization: 43235783Skib */ 44235783Skib 45235783Skib#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46235783Skib 47235783Skib#define DRIVER_NAME "i915" 48235783Skib#define DRIVER_DESC "Intel Graphics" 49235783Skib#define DRIVER_DATE "20080730" 50235783Skib 51235783SkibMALLOC_DECLARE(DRM_I915_GEM); 52235783Skib 53235783Skibenum pipe { 54235783Skib PIPE_A = 0, 55235783Skib PIPE_B, 56235783Skib PIPE_C, 57235783Skib I915_MAX_PIPES 58235783Skib}; 59235783Skib#define pipe_name(p) ((p) + 'A') 60235783Skib 61296548Sdumbbellenum transcoder { 62296548Sdumbbell TRANSCODER_A = 0, 63296548Sdumbbell TRANSCODER_B, 64296548Sdumbbell TRANSCODER_C, 65296548Sdumbbell TRANSCODER_EDP = 0xF, 66296548Sdumbbell}; 67296548Sdumbbell#define transcoder_name(t) ((t) + 'A') 68296548Sdumbbell 69235783Skibenum plane { 70235783Skib PLANE_A = 0, 71235783Skib PLANE_B, 72235783Skib PLANE_C, 73235783Skib}; 74235783Skib#define plane_name(p) ((p) + 'A') 75235783Skib 76277487Skibenum port { 77277487Skib PORT_A = 0, 78277487Skib PORT_B, 79277487Skib PORT_C, 80277487Skib PORT_D, 81277487Skib PORT_E, 82277487Skib I915_MAX_PORTS 83277487Skib}; 84277487Skib#define port_name(p) ((p) + 'A') 85235783Skib 86277487Skib#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 87277487Skib 88235783Skib#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 89235783Skib 90296548Sdumbbell#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 91296548Sdumbbell list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 92296548Sdumbbell if ((intel_encoder)->base.crtc == (__crtc)) 93296548Sdumbbell 94277487Skibstruct intel_pch_pll { 95277487Skib int refcount; /* count of number of CRTCs sharing this PLL */ 96277487Skib int active; /* count of number of active CRTCs (i.e. DPMS on) */ 97277487Skib bool on; /* is the PLL actually active? Disabled during modeset */ 98277487Skib int pll_reg; 99277487Skib int fp0_reg; 100277487Skib int fp1_reg; 101277487Skib}; 102277487Skib#define I915_NUM_PLLS 2 103277487Skib 104296548Sdumbbellstruct intel_ddi_plls { 105296548Sdumbbell int spll_refcount; 106296548Sdumbbell int wrpll1_refcount; 107296548Sdumbbell int wrpll2_refcount; 108296548Sdumbbell}; 109296548Sdumbbell 110235783Skib/* Interface history: 111235783Skib * 112235783Skib * 1.1: Original. 113235783Skib * 1.2: Add Power Management 114235783Skib * 1.3: Add vblank support 115235783Skib * 1.4: Fix cmdbuffer path, add heap destroy 116235783Skib * 1.5: Add vblank pipe configuration 117235783Skib * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 118235783Skib * - Support vertical blank on secondary display pipe 119235783Skib */ 120235783Skib#define DRIVER_MAJOR 1 121235783Skib#define DRIVER_MINOR 6 122235783Skib#define DRIVER_PATCHLEVEL 0 123235783Skib 124235783Skib#define WATCH_COHERENCY 0 125296548Sdumbbell#define WATCH_LISTS 0 126296548Sdumbbell#define WATCH_GTT 0 127235783Skib 128235783Skib#define I915_GEM_PHYS_CURSOR_0 1 129235783Skib#define I915_GEM_PHYS_CURSOR_1 2 130235783Skib#define I915_GEM_PHYS_OVERLAY_REGS 3 131235783Skib#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 132235783Skib 133235783Skibstruct drm_i915_gem_phys_object { 134235783Skib int id; 135235783Skib drm_dma_handle_t *handle; 136235783Skib struct drm_i915_gem_object *cur_obj; 137235783Skib}; 138235783Skib 139296548Sdumbbellstruct opregion_header; 140296548Sdumbbellstruct opregion_acpi; 141296548Sdumbbellstruct opregion_swsci; 142296548Sdumbbellstruct opregion_asle; 143235783Skibstruct drm_i915_private; 144235783Skib 145296548Sdumbbellstruct intel_opregion { 146296548Sdumbbell struct opregion_header __iomem *header; 147296548Sdumbbell struct opregion_acpi __iomem *acpi; 148296548Sdumbbell struct opregion_swsci __iomem *swsci; 149296548Sdumbbell struct opregion_asle __iomem *asle; 150296548Sdumbbell void __iomem *vbt; 151296548Sdumbbell u32 __iomem *lid_state; 152296548Sdumbbell}; 153296548Sdumbbell#define OPREGION_SIZE (8*1024) 154296548Sdumbbell 155296548Sdumbbellstruct intel_overlay; 156296548Sdumbbellstruct intel_overlay_error_state; 157296548Sdumbbell 158296548Sdumbbellstruct drm_i915_master_private { 159296548Sdumbbell drm_local_map_t *sarea; 160296548Sdumbbell struct _drm_i915_sarea *sarea_priv; 161296548Sdumbbell}; 162296548Sdumbbell#define I915_FENCE_REG_NONE -1 163296548Sdumbbell#define I915_MAX_NUM_FENCES 16 164296548Sdumbbell/* 16 fences + sign bit for FENCE_REG_NONE */ 165296548Sdumbbell#define I915_MAX_NUM_FENCE_BITS 5 166296548Sdumbbell 167296548Sdumbbellstruct drm_i915_fence_reg { 168296548Sdumbbell struct list_head lru_list; 169296548Sdumbbell struct drm_i915_gem_object *obj; 170296548Sdumbbell int pin_count; 171296548Sdumbbell}; 172296548Sdumbbell 173296548Sdumbbellstruct sdvo_device_mapping { 174296548Sdumbbell u8 initialized; 175296548Sdumbbell u8 dvo_port; 176296548Sdumbbell u8 slave_addr; 177296548Sdumbbell u8 dvo_wiring; 178296548Sdumbbell u8 i2c_pin; 179296548Sdumbbell u8 ddc_pin; 180296548Sdumbbell}; 181296548Sdumbbell 182296548Sdumbbellstruct intel_display_error_state; 183296548Sdumbbell 184296548Sdumbbellstruct drm_i915_error_state { 185296548Sdumbbell u_int ref; 186296548Sdumbbell u32 eir; 187296548Sdumbbell u32 pgtbl_er; 188296548Sdumbbell u32 ier; 189296548Sdumbbell u32 ccid; 190296548Sdumbbell u32 derrmr; 191296548Sdumbbell u32 forcewake; 192296548Sdumbbell bool waiting[I915_NUM_RINGS]; 193296548Sdumbbell u32 pipestat[I915_MAX_PIPES]; 194296548Sdumbbell u32 tail[I915_NUM_RINGS]; 195296548Sdumbbell u32 head[I915_NUM_RINGS]; 196296548Sdumbbell u32 ctl[I915_NUM_RINGS]; 197296548Sdumbbell u32 ipeir[I915_NUM_RINGS]; 198296548Sdumbbell u32 ipehr[I915_NUM_RINGS]; 199296548Sdumbbell u32 instdone[I915_NUM_RINGS]; 200296548Sdumbbell u32 acthd[I915_NUM_RINGS]; 201296548Sdumbbell u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 202296548Sdumbbell u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 203296548Sdumbbell u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 204296548Sdumbbell /* our own tracking of ring head and tail */ 205296548Sdumbbell u32 cpu_ring_head[I915_NUM_RINGS]; 206296548Sdumbbell u32 cpu_ring_tail[I915_NUM_RINGS]; 207296548Sdumbbell u32 error; /* gen6+ */ 208296548Sdumbbell u32 err_int; /* gen7 */ 209296548Sdumbbell u32 instpm[I915_NUM_RINGS]; 210296548Sdumbbell u32 instps[I915_NUM_RINGS]; 211296548Sdumbbell u32 extra_instdone[I915_NUM_INSTDONE_REG]; 212296548Sdumbbell u32 seqno[I915_NUM_RINGS]; 213296548Sdumbbell u64 bbaddr; 214296548Sdumbbell u32 fault_reg[I915_NUM_RINGS]; 215296548Sdumbbell u32 done_reg; 216296548Sdumbbell u32 faddr[I915_NUM_RINGS]; 217296548Sdumbbell u64 fence[I915_MAX_NUM_FENCES]; 218296548Sdumbbell struct timeval time; 219296548Sdumbbell struct drm_i915_error_ring { 220296548Sdumbbell struct drm_i915_error_object { 221296548Sdumbbell int page_count; 222296548Sdumbbell u32 gtt_offset; 223296548Sdumbbell u32 *pages[0]; 224296548Sdumbbell } *ringbuffer, *batchbuffer; 225296548Sdumbbell struct drm_i915_error_request { 226296548Sdumbbell long jiffies; 227296548Sdumbbell u32 seqno; 228296548Sdumbbell u32 tail; 229296548Sdumbbell } *requests; 230296548Sdumbbell int num_requests; 231296548Sdumbbell } ring[I915_NUM_RINGS]; 232296548Sdumbbell struct drm_i915_error_buffer { 233296548Sdumbbell u32 size; 234296548Sdumbbell u32 name; 235296548Sdumbbell u32 rseqno, wseqno; 236296548Sdumbbell u32 gtt_offset; 237296548Sdumbbell u32 read_domains; 238296548Sdumbbell u32 write_domain; 239296548Sdumbbell s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 240296548Sdumbbell s32 pinned:2; 241296548Sdumbbell u32 tiling:2; 242296548Sdumbbell u32 dirty:1; 243296548Sdumbbell u32 purgeable:1; 244296548Sdumbbell s32 ring:4; 245296548Sdumbbell u32 cache_level:2; 246296548Sdumbbell } *active_bo, *pinned_bo; 247296548Sdumbbell u32 active_bo_count, pinned_bo_count; 248296548Sdumbbell struct intel_overlay_error_state *overlay; 249296548Sdumbbell struct intel_display_error_state *display; 250296548Sdumbbell}; 251296548Sdumbbell 252235783Skibstruct drm_i915_display_funcs { 253235783Skib bool (*fbc_enabled)(struct drm_device *dev); 254235783Skib void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 255235783Skib void (*disable_fbc)(struct drm_device *dev); 256235783Skib int (*get_display_clock_speed)(struct drm_device *dev); 257235783Skib int (*get_fifo_size)(struct drm_device *dev, int plane); 258235783Skib void (*update_wm)(struct drm_device *dev); 259235783Skib void (*update_sprite_wm)(struct drm_device *dev, int pipe, 260235783Skib uint32_t sprite_width, int pixel_size); 261277487Skib void (*update_linetime_wm)(struct drm_device *dev, int pipe, 262277487Skib struct drm_display_mode *mode); 263296548Sdumbbell void (*modeset_global_resources)(struct drm_device *dev); 264235783Skib int (*crtc_mode_set)(struct drm_crtc *crtc, 265235783Skib struct drm_display_mode *mode, 266235783Skib struct drm_display_mode *adjusted_mode, 267235783Skib int x, int y, 268235783Skib struct drm_framebuffer *old_fb); 269296548Sdumbbell void (*crtc_enable)(struct drm_crtc *crtc); 270296548Sdumbbell void (*crtc_disable)(struct drm_crtc *crtc); 271277487Skib void (*off)(struct drm_crtc *crtc); 272235783Skib void (*write_eld)(struct drm_connector *connector, 273235783Skib struct drm_crtc *crtc); 274235783Skib void (*fdi_link_train)(struct drm_crtc *crtc); 275235783Skib void (*init_clock_gating)(struct drm_device *dev); 276235783Skib int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 277235783Skib struct drm_framebuffer *fb, 278235783Skib struct drm_i915_gem_object *obj); 279235783Skib int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 280235783Skib int x, int y); 281235783Skib /* clock updates for mode set */ 282235783Skib /* cursor updates */ 283235783Skib /* render clock increase/decrease */ 284235783Skib /* display clock increase/decrease */ 285235783Skib /* pll clock increase/decrease */ 286235783Skib}; 287235783Skib 288296548Sdumbbellstruct drm_i915_gt_funcs { 289296548Sdumbbell void (*force_wake_get)(struct drm_i915_private *dev_priv); 290296548Sdumbbell void (*force_wake_put)(struct drm_i915_private *dev_priv); 291296548Sdumbbell}; 292296548Sdumbbell 293296548Sdumbbell#define DEV_INFO_FLAGS \ 294296548Sdumbbell DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 295296548Sdumbbell DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 296296548Sdumbbell DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 297296548Sdumbbell DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 298296548Sdumbbell DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 299296548Sdumbbell DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 300296548Sdumbbell DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 301296548Sdumbbell DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 302296548Sdumbbell DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 303296548Sdumbbell DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 304296548Sdumbbell DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 305296548Sdumbbell DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 306296548Sdumbbell DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 307296548Sdumbbell DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 308296548Sdumbbell DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 309296548Sdumbbell DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 310296548Sdumbbell DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 311296548Sdumbbell DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 312296548Sdumbbell DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 313296548Sdumbbell DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 314296548Sdumbbell DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 315296548Sdumbbell DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 316296548Sdumbbell DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 317296548Sdumbbell DEV_INFO_FLAG(has_llc) 318296548Sdumbbell 319235783Skibstruct intel_device_info { 320235783Skib u8 gen; 321235783Skib u8 is_mobile:1; 322235783Skib u8 is_i85x:1; 323235783Skib u8 is_i915g:1; 324235783Skib u8 is_i945gm:1; 325235783Skib u8 is_g33:1; 326235783Skib u8 need_gfx_hws:1; 327235783Skib u8 is_g4x:1; 328235783Skib u8 is_pineview:1; 329235783Skib u8 is_broadwater:1; 330235783Skib u8 is_crestline:1; 331235783Skib u8 is_ivybridge:1; 332277487Skib u8 is_valleyview:1; 333296548Sdumbbell u8 has_force_wake:1; 334277487Skib u8 is_haswell:1; 335235783Skib u8 has_fbc:1; 336235783Skib u8 has_pipe_cxsr:1; 337235783Skib u8 has_hotplug:1; 338235783Skib u8 cursor_needs_physical:1; 339235783Skib u8 has_overlay:1; 340235783Skib u8 overlay_needs_physical:1; 341235783Skib u8 supports_tv:1; 342235783Skib u8 has_bsd_ring:1; 343235783Skib u8 has_blt_ring:1; 344235783Skib u8 has_llc:1; 345235783Skib}; 346235783Skib 347235783Skib#define I915_PPGTT_PD_ENTRIES 512 348235783Skib#define I915_PPGTT_PT_ENTRIES 1024 349235783Skibstruct i915_hw_ppgtt { 350296548Sdumbbell struct drm_device *dev; 351235783Skib unsigned num_pd_entries; 352235783Skib vm_page_t *pt_pages; 353235783Skib uint32_t pd_offset; 354235783Skib vm_paddr_t *pt_dma_addr; 355235783Skib vm_paddr_t scratch_page_dma_addr; 356235783Skib}; 357235783Skib 358271705Sdumbbell 359271705Sdumbbell/* This must match up with the value previously used for execbuf2.rsvd1. */ 360271705Sdumbbell#define DEFAULT_CONTEXT_ID 0 361271705Sdumbbellstruct i915_hw_context { 362271705Sdumbbell uint32_t id; 363271705Sdumbbell bool is_initialized; 364271705Sdumbbell struct drm_i915_file_private *file_priv; 365271705Sdumbbell struct intel_ring_buffer *ring; 366271705Sdumbbell struct drm_i915_gem_object *obj; 367271705Sdumbbell}; 368271705Sdumbbell 369235783Skibenum no_fbc_reason { 370235783Skib FBC_NO_OUTPUT, /* no outputs enabled to compress */ 371235783Skib FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 372235783Skib FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 373235783Skib FBC_MODE_TOO_LARGE, /* mode too large for compression */ 374235783Skib FBC_BAD_PLANE, /* fbc not supported on plane */ 375235783Skib FBC_NOT_TILED, /* buffer not tiled */ 376235783Skib FBC_MULTIPLE_PIPES, /* more than one pipe active */ 377235783Skib FBC_MODULE_PARAM, 378235783Skib}; 379235783Skib 380235783Skibenum intel_pch { 381296548Sdumbbell PCH_NONE = 0, /* No PCH present */ 382235783Skib PCH_IBX, /* Ibexpeak PCH */ 383235783Skib PCH_CPT, /* Cougarpoint PCH */ 384277487Skib PCH_LPT, /* Lynxpoint PCH */ 385235783Skib}; 386235783Skib 387296548Sdumbbellenum intel_sbi_destination { 388296548Sdumbbell SBI_ICLK, 389296548Sdumbbell SBI_MPHY, 390296548Sdumbbell}; 391296548Sdumbbell 392235783Skib#define QUIRK_PIPEA_FORCE (1<<0) 393235783Skib#define QUIRK_LVDS_SSC_DISABLE (1<<1) 394277487Skib#define QUIRK_INVERT_BRIGHTNESS (1<<2) 395235783Skib 396235783Skibstruct intel_fbdev; 397235783Skibstruct intel_fbc_work; 398235783Skib 399296548Sdumbbellstruct intel_gmbus { 400296548Sdumbbell device_t gmbus_bridge; 401296548Sdumbbell device_t gmbus; 402296548Sdumbbell device_t bbbus_bridge; 403296548Sdumbbell device_t bbbus; 404296548Sdumbbell u32 force_bit; 405296548Sdumbbell u32 reg0; 406296548Sdumbbell u32 gpio_reg; 407296548Sdumbbell struct drm_i915_private *dev_priv; 408296548Sdumbbell}; 409235783Skib 410296548Sdumbbellstruct i915_suspend_saved_registers { 411235783Skib u8 saveLBB; 412235783Skib u32 saveDSPACNTR; 413235783Skib u32 saveDSPBCNTR; 414235783Skib u32 saveDSPARB; 415235783Skib u32 savePIPEACONF; 416235783Skib u32 savePIPEBCONF; 417235783Skib u32 savePIPEASRC; 418235783Skib u32 savePIPEBSRC; 419235783Skib u32 saveFPA0; 420235783Skib u32 saveFPA1; 421235783Skib u32 saveDPLL_A; 422235783Skib u32 saveDPLL_A_MD; 423235783Skib u32 saveHTOTAL_A; 424235783Skib u32 saveHBLANK_A; 425235783Skib u32 saveHSYNC_A; 426235783Skib u32 saveVTOTAL_A; 427235783Skib u32 saveVBLANK_A; 428235783Skib u32 saveVSYNC_A; 429235783Skib u32 saveBCLRPAT_A; 430235783Skib u32 saveTRANSACONF; 431235783Skib u32 saveTRANS_HTOTAL_A; 432235783Skib u32 saveTRANS_HBLANK_A; 433235783Skib u32 saveTRANS_HSYNC_A; 434235783Skib u32 saveTRANS_VTOTAL_A; 435235783Skib u32 saveTRANS_VBLANK_A; 436235783Skib u32 saveTRANS_VSYNC_A; 437235783Skib u32 savePIPEASTAT; 438235783Skib u32 saveDSPASTRIDE; 439235783Skib u32 saveDSPASIZE; 440235783Skib u32 saveDSPAPOS; 441235783Skib u32 saveDSPAADDR; 442235783Skib u32 saveDSPASURF; 443235783Skib u32 saveDSPATILEOFF; 444235783Skib u32 savePFIT_PGM_RATIOS; 445235783Skib u32 saveBLC_HIST_CTL; 446235783Skib u32 saveBLC_PWM_CTL; 447235783Skib u32 saveBLC_PWM_CTL2; 448235783Skib u32 saveBLC_CPU_PWM_CTL; 449235783Skib u32 saveBLC_CPU_PWM_CTL2; 450235783Skib u32 saveFPB0; 451235783Skib u32 saveFPB1; 452235783Skib u32 saveDPLL_B; 453235783Skib u32 saveDPLL_B_MD; 454235783Skib u32 saveHTOTAL_B; 455235783Skib u32 saveHBLANK_B; 456235783Skib u32 saveHSYNC_B; 457235783Skib u32 saveVTOTAL_B; 458235783Skib u32 saveVBLANK_B; 459235783Skib u32 saveVSYNC_B; 460235783Skib u32 saveBCLRPAT_B; 461235783Skib u32 saveTRANSBCONF; 462235783Skib u32 saveTRANS_HTOTAL_B; 463235783Skib u32 saveTRANS_HBLANK_B; 464235783Skib u32 saveTRANS_HSYNC_B; 465235783Skib u32 saveTRANS_VTOTAL_B; 466235783Skib u32 saveTRANS_VBLANK_B; 467235783Skib u32 saveTRANS_VSYNC_B; 468235783Skib u32 savePIPEBSTAT; 469235783Skib u32 saveDSPBSTRIDE; 470235783Skib u32 saveDSPBSIZE; 471235783Skib u32 saveDSPBPOS; 472235783Skib u32 saveDSPBADDR; 473235783Skib u32 saveDSPBSURF; 474235783Skib u32 saveDSPBTILEOFF; 475235783Skib u32 saveVGA0; 476235783Skib u32 saveVGA1; 477235783Skib u32 saveVGA_PD; 478235783Skib u32 saveVGACNTRL; 479235783Skib u32 saveADPA; 480235783Skib u32 saveLVDS; 481235783Skib u32 savePP_ON_DELAYS; 482235783Skib u32 savePP_OFF_DELAYS; 483235783Skib u32 saveDVOA; 484235783Skib u32 saveDVOB; 485235783Skib u32 saveDVOC; 486235783Skib u32 savePP_ON; 487235783Skib u32 savePP_OFF; 488235783Skib u32 savePP_CONTROL; 489235783Skib u32 savePP_DIVISOR; 490235783Skib u32 savePFIT_CONTROL; 491235783Skib u32 save_palette_a[256]; 492235783Skib u32 save_palette_b[256]; 493235783Skib u32 saveDPFC_CB_BASE; 494235783Skib u32 saveFBC_CFB_BASE; 495235783Skib u32 saveFBC_LL_BASE; 496235783Skib u32 saveFBC_CONTROL; 497235783Skib u32 saveFBC_CONTROL2; 498235783Skib u32 saveIER; 499235783Skib u32 saveIIR; 500235783Skib u32 saveIMR; 501235783Skib u32 saveDEIER; 502235783Skib u32 saveDEIMR; 503235783Skib u32 saveGTIER; 504235783Skib u32 saveGTIMR; 505235783Skib u32 saveFDI_RXA_IMR; 506235783Skib u32 saveFDI_RXB_IMR; 507235783Skib u32 saveCACHE_MODE_0; 508235783Skib u32 saveMI_ARB_STATE; 509235783Skib u32 saveSWF0[16]; 510235783Skib u32 saveSWF1[16]; 511235783Skib u32 saveSWF2[3]; 512235783Skib u8 saveMSR; 513235783Skib u8 saveSR[8]; 514235783Skib u8 saveGR[25]; 515235783Skib u8 saveAR_INDEX; 516235783Skib u8 saveAR[21]; 517235783Skib u8 saveDACMASK; 518235783Skib u8 saveCR[37]; 519235783Skib uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 520235783Skib u32 saveCURACNTR; 521235783Skib u32 saveCURAPOS; 522235783Skib u32 saveCURABASE; 523235783Skib u32 saveCURBCNTR; 524235783Skib u32 saveCURBPOS; 525235783Skib u32 saveCURBBASE; 526235783Skib u32 saveCURSIZE; 527235783Skib u32 saveDP_B; 528235783Skib u32 saveDP_C; 529235783Skib u32 saveDP_D; 530235783Skib u32 savePIPEA_GMCH_DATA_M; 531235783Skib u32 savePIPEB_GMCH_DATA_M; 532235783Skib u32 savePIPEA_GMCH_DATA_N; 533235783Skib u32 savePIPEB_GMCH_DATA_N; 534235783Skib u32 savePIPEA_DP_LINK_M; 535235783Skib u32 savePIPEB_DP_LINK_M; 536235783Skib u32 savePIPEA_DP_LINK_N; 537235783Skib u32 savePIPEB_DP_LINK_N; 538235783Skib u32 saveFDI_RXA_CTL; 539235783Skib u32 saveFDI_TXA_CTL; 540235783Skib u32 saveFDI_RXB_CTL; 541235783Skib u32 saveFDI_TXB_CTL; 542235783Skib u32 savePFA_CTL_1; 543235783Skib u32 savePFB_CTL_1; 544235783Skib u32 savePFA_WIN_SZ; 545235783Skib u32 savePFB_WIN_SZ; 546235783Skib u32 savePFA_WIN_POS; 547235783Skib u32 savePFB_WIN_POS; 548235783Skib u32 savePCH_DREF_CONTROL; 549235783Skib u32 saveDISP_ARB_CTL; 550235783Skib u32 savePIPEA_DATA_M1; 551235783Skib u32 savePIPEA_DATA_N1; 552235783Skib u32 savePIPEA_LINK_M1; 553235783Skib u32 savePIPEA_LINK_N1; 554235783Skib u32 savePIPEB_DATA_M1; 555235783Skib u32 savePIPEB_DATA_N1; 556235783Skib u32 savePIPEB_LINK_M1; 557235783Skib u32 savePIPEB_LINK_N1; 558235783Skib u32 saveMCHBAR_RENDER_STANDBY; 559235783Skib u32 savePCH_PORT_HOTPLUG; 560296548Sdumbbell}; 561235783Skib 562296548Sdumbbellstruct intel_gen6_power_mgmt { 563296548Sdumbbell struct task work; 564296548Sdumbbell u32 pm_iir; 565296548Sdumbbell /* lock - irqsave spinlock that protectects the work_struct and 566296548Sdumbbell * pm_iir. */ 567296548Sdumbbell struct mtx lock; 568296548Sdumbbell 569296548Sdumbbell /* The below variables an all the rps hw state are protected by 570296548Sdumbbell * dev->struct mutext. */ 571296548Sdumbbell u8 cur_delay; 572296548Sdumbbell u8 min_delay; 573296548Sdumbbell u8 max_delay; 574296548Sdumbbell 575296548Sdumbbell struct timeout_task delayed_resume_work; 576296548Sdumbbell 577296548Sdumbbell /* 578296548Sdumbbell * Protects RPS/RC6 register access and PCU communication. 579296548Sdumbbell * Must be taken after struct_mutex if nested. 580296548Sdumbbell */ 581296548Sdumbbell struct sx hw_lock; 582296548Sdumbbell}; 583296548Sdumbbell 584296548Sdumbbellstruct intel_ilk_power_mgmt { 585296548Sdumbbell u8 cur_delay; 586296548Sdumbbell u8 min_delay; 587296548Sdumbbell u8 max_delay; 588296548Sdumbbell u8 fmax; 589296548Sdumbbell u8 fstart; 590296548Sdumbbell 591296548Sdumbbell u64 last_count1; 592296548Sdumbbell unsigned long last_time1; 593296548Sdumbbell unsigned long chipset_power; 594296548Sdumbbell u64 last_count2; 595296548Sdumbbell struct timespec last_time2; 596296548Sdumbbell unsigned long gfx_power; 597296548Sdumbbell u8 corr; 598296548Sdumbbell 599296548Sdumbbell int c_m; 600296548Sdumbbell int r_t; 601296548Sdumbbell 602296548Sdumbbell struct drm_i915_gem_object *pwrctx; 603296548Sdumbbell struct drm_i915_gem_object *renderctx; 604296548Sdumbbell}; 605296548Sdumbbell 606296548Sdumbbellstruct i915_dri1_state { 607296548Sdumbbell unsigned allow_batchbuffer : 1; 608296548Sdumbbell u32 __iomem *gfx_hws_cpu_addr; 609296548Sdumbbell 610296548Sdumbbell unsigned int cpp; 611296548Sdumbbell int back_offset; 612296548Sdumbbell int front_offset; 613296548Sdumbbell int current_page; 614296548Sdumbbell int page_flipping; 615296548Sdumbbell 616296548Sdumbbell uint32_t counter; 617296548Sdumbbell}; 618296548Sdumbbell 619296548Sdumbbellstruct intel_l3_parity { 620296548Sdumbbell u32 *remap_info; 621296548Sdumbbell struct task error_work; 622296548Sdumbbell}; 623296548Sdumbbell 624296548Sdumbbelltypedef struct drm_i915_private { 625296548Sdumbbell struct drm_device *dev; 626296548Sdumbbell 627296548Sdumbbell const struct intel_device_info *info; 628296548Sdumbbell 629296548Sdumbbell int relative_constants_mode; 630296548Sdumbbell 631296548Sdumbbell /* FIXME Linux<->FreeBSD: "void *regs" on Linux. */ 632296548Sdumbbell drm_local_map_t *mmio_map; 633296548Sdumbbell 634296548Sdumbbell struct drm_i915_gt_funcs gt; 635296548Sdumbbell /** gt_fifo_count and the subsequent register write are synchronized 636296548Sdumbbell * with dev->struct_mutex. */ 637296548Sdumbbell unsigned gt_fifo_count; 638296548Sdumbbell /** forcewake_count is protected by gt_lock */ 639296548Sdumbbell unsigned forcewake_count; 640296548Sdumbbell /** gt_lock is also taken in irq contexts. */ 641296548Sdumbbell struct mtx gt_lock; 642296548Sdumbbell 643296548Sdumbbell struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 644296548Sdumbbell 645296548Sdumbbell /** gmbus_mutex protects against concurrent usage of the single hw gmbus 646296548Sdumbbell * controller on different i2c buses. */ 647296548Sdumbbell struct sx gmbus_mutex; 648296548Sdumbbell 649296548Sdumbbell /** 650296548Sdumbbell * Base address of the gmbus and gpio block. 651296548Sdumbbell */ 652296548Sdumbbell uint32_t gpio_mmio_base; 653296548Sdumbbell 654296548Sdumbbell device_t bridge_dev; 655296548Sdumbbell struct intel_ring_buffer ring[I915_NUM_RINGS]; 656296548Sdumbbell uint32_t next_seqno; 657296548Sdumbbell 658296548Sdumbbell drm_dma_handle_t *status_page_dmah; 659296548Sdumbbell int mch_res_rid; 660296548Sdumbbell struct resource *mch_res; 661296548Sdumbbell 662296548Sdumbbell atomic_t irq_received; 663296548Sdumbbell 664296548Sdumbbell /* protects the irq masks */ 665296548Sdumbbell struct mtx irq_lock; 666296548Sdumbbell 667296548Sdumbbell /* DPIO indirect register protection */ 668296548Sdumbbell struct sx dpio_lock; 669296548Sdumbbell 670296548Sdumbbell /** Cached value of IMR to avoid reads in updating the bitfield */ 671296548Sdumbbell u32 pipestat[2]; 672296548Sdumbbell u32 irq_mask; 673296548Sdumbbell u32 gt_irq_mask; 674296548Sdumbbell u32 pch_irq_mask; 675296548Sdumbbell 676296548Sdumbbell u32 hotplug_supported_mask; 677296548Sdumbbell struct task hotplug_work; 678296548Sdumbbell 679296548Sdumbbell int num_pipe; 680296548Sdumbbell int num_pch_pll; 681296548Sdumbbell 682296548Sdumbbell /* For hangcheck timer */ 683296548Sdumbbell#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 684296548Sdumbbell#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 685296548Sdumbbell struct callout hangcheck_timer; 686296548Sdumbbell int hangcheck_count; 687296548Sdumbbell uint32_t last_acthd[I915_NUM_RINGS]; 688296548Sdumbbell uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 689296548Sdumbbell 690296548Sdumbbell unsigned int stop_rings; 691296548Sdumbbell 692296548Sdumbbell unsigned long cfb_size; 693296548Sdumbbell unsigned int cfb_fb; 694296548Sdumbbell enum plane cfb_plane; 695296548Sdumbbell int cfb_y; 696296548Sdumbbell struct intel_fbc_work *fbc_work; 697296548Sdumbbell 698296548Sdumbbell struct intel_opregion opregion; 699296548Sdumbbell 700296548Sdumbbell /* overlay */ 701296548Sdumbbell struct intel_overlay *overlay; 702296548Sdumbbell bool sprite_scaling_enabled; 703296548Sdumbbell 704296548Sdumbbell /* LVDS info */ 705296548Sdumbbell int backlight_level; /* restore backlight to this value */ 706296548Sdumbbell bool backlight_enabled; 707296548Sdumbbell struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 708296548Sdumbbell struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 709296548Sdumbbell 710296548Sdumbbell /* Feature bits from the VBIOS */ 711296548Sdumbbell unsigned int int_tv_support:1; 712296548Sdumbbell unsigned int lvds_dither:1; 713296548Sdumbbell unsigned int lvds_vbt:1; 714296548Sdumbbell unsigned int int_crt_support:1; 715296548Sdumbbell unsigned int lvds_use_ssc:1; 716296548Sdumbbell unsigned int display_clock_mode:1; 717296548Sdumbbell unsigned int fdi_rx_polarity_inverted:1; 718296548Sdumbbell int lvds_ssc_freq; 719296548Sdumbbell unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 720296548Sdumbbell unsigned int lvds_val; /* used for checking LVDS channel mode */ 721235783Skib struct { 722296548Sdumbbell int rate; 723296548Sdumbbell int lanes; 724296548Sdumbbell int preemphasis; 725296548Sdumbbell int vswing; 726296548Sdumbbell 727296548Sdumbbell bool initialized; 728296548Sdumbbell bool support; 729296548Sdumbbell int bpp; 730296548Sdumbbell struct edp_power_seq pps; 731296548Sdumbbell } edp; 732296548Sdumbbell bool no_aux_handshake; 733296548Sdumbbell 734296548Sdumbbell int crt_ddc_pin; 735296548Sdumbbell struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 736296548Sdumbbell int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 737296548Sdumbbell int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 738296548Sdumbbell 739296548Sdumbbell unsigned int fsb_freq, mem_freq, is_ddr3; 740296548Sdumbbell 741296548Sdumbbell struct mtx error_lock; 742296548Sdumbbell /* Protected by dev->error_lock. */ 743296548Sdumbbell struct drm_i915_error_state *first_error; 744296548Sdumbbell struct task error_work; 745296548Sdumbbell struct completion error_completion; 746296548Sdumbbell struct taskqueue *wq; 747296548Sdumbbell 748296548Sdumbbell /* Display functions */ 749296548Sdumbbell struct drm_i915_display_funcs display; 750296548Sdumbbell 751296548Sdumbbell /* PCH chipset type */ 752296548Sdumbbell enum intel_pch pch_type; 753296548Sdumbbell unsigned short pch_id; 754296548Sdumbbell 755296548Sdumbbell unsigned long quirks; 756296548Sdumbbell 757296548Sdumbbell /* Register state */ 758296548Sdumbbell bool modeset_on_lid; 759296548Sdumbbell 760296548Sdumbbell struct { 761296548Sdumbbell /** Bridge to intel-gtt-ko */ 762296548Sdumbbell struct intel_gtt *gtt; 763235783Skib /** Memory allocator for GTT stolen memory */ 764235783Skib struct drm_mm stolen; 765235783Skib /** Memory allocator for GTT */ 766235783Skib struct drm_mm gtt_space; 767235783Skib /** List of all objects in gtt_space. Used to restore gtt 768235783Skib * mappings on resume */ 769296548Sdumbbell struct list_head bound_list; 770296548Sdumbbell /** 771296548Sdumbbell * List of objects which are not bound to the GTT (thus 772296548Sdumbbell * are idle and not used by the GPU) but still have 773296548Sdumbbell * (presumably uncached) pages still attached. 774296548Sdumbbell */ 775296548Sdumbbell struct list_head unbound_list; 776235783Skib 777235783Skib /** Usable portion of the GTT for GEM */ 778235783Skib unsigned long gtt_start; 779235783Skib unsigned long gtt_mappable_end; 780235783Skib unsigned long gtt_end; 781296548Sdumbbell unsigned long stolen_base; /* limited to low memory (32-bit) */ 782235783Skib 783296548Sdumbbell#ifdef __linux__ 784296548Sdumbbell struct io_mapping *gtt_mapping; 785296548Sdumbbell#endif 786296548Sdumbbell vm_paddr_t gtt_base_addr; 787296548Sdumbbell int gtt_mtrr; 788296548Sdumbbell 789235783Skib /** PPGTT used for aliasing the PPGTT with the GTT */ 790235783Skib struct i915_hw_ppgtt *aliasing_ppgtt; 791235783Skib 792296548Sdumbbell eventhandler_tag inactive_shrinker; 793296548Sdumbbell bool shrinker_no_lock_stealing; 794296548Sdumbbell 795235783Skib /** 796296548Sdumbbell * List of objects currently involved in rendering. 797235783Skib * 798235783Skib * Includes buffers having the contents of their GPU caches 799235783Skib * flushed, not necessarily primitives. last_rendering_seqno 800235783Skib * represents when the rendering involved will be completed. 801235783Skib * 802235783Skib * A reference is held on the buffer while on this list. 803235783Skib */ 804235783Skib struct list_head active_list; 805235783Skib 806235783Skib /** 807235783Skib * LRU list of objects which are not in the ringbuffer and 808235783Skib * are ready to unbind, but are still in the GTT. 809235783Skib * 810235783Skib * last_rendering_seqno is 0 while an object is in this list. 811235783Skib * 812235783Skib * A reference is not held on the buffer while on this list, 813235783Skib * as merely being GTT-bound shouldn't prevent its being 814235783Skib * freed, and we'll pull it off the list in the free path. 815235783Skib */ 816235783Skib struct list_head inactive_list; 817235783Skib 818235783Skib /** LRU list of objects with fence regs on them. */ 819235783Skib struct list_head fence_list; 820235783Skib 821235783Skib /** 822235783Skib * We leave the user IRQ off as much as possible, 823235783Skib * but this means that requests will finish and never 824235783Skib * be retired once the system goes idle. Set a timer to 825235783Skib * fire periodically while the ring is running. When it 826235783Skib * fires, go retire requests. 827235783Skib */ 828296548Sdumbbell struct timeout_task retire_work; 829235783Skib 830296548Sdumbbell /** 831235783Skib * Are we in a non-interruptible section of code like 832235783Skib * modesetting? 833235783Skib */ 834235783Skib bool interruptible; 835235783Skib 836235783Skib /** 837235783Skib * Flag if the X Server, and thus DRM, is not currently in 838235783Skib * control of the device. 839235783Skib * 840235783Skib * This is set between LeaveVT and EnterVT. It needs to be 841235783Skib * replaced with a semaphore. It also needs to be 842235783Skib * transitioned away from for kernel modesetting. 843235783Skib */ 844235783Skib int suspended; 845235783Skib 846235783Skib /** 847235783Skib * Flag if the hardware appears to be wedged. 848235783Skib * 849235783Skib * This is set when attempts to idle the device timeout. 850296548Sdumbbell * It prevents command submission from occurring and makes 851235783Skib * every pending request fail 852235783Skib */ 853296548Sdumbbell atomic_t wedged; 854235783Skib 855235783Skib /** Bit 6 swizzling required for X tiling */ 856235783Skib uint32_t bit_6_swizzle_x; 857235783Skib /** Bit 6 swizzling required for Y tiling */ 858235783Skib uint32_t bit_6_swizzle_y; 859235783Skib 860235783Skib /* storage for physical objects */ 861235783Skib struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 862235783Skib 863235783Skib /* accounting, useful for userland debugging */ 864235783Skib size_t gtt_total; 865235783Skib size_t mappable_gtt_total; 866235783Skib size_t object_memory; 867235783Skib u32 object_count; 868235783Skib } mm; 869235783Skib 870277487Skib /* Kernel Modesetting */ 871277487Skib 872235783Skib struct sdvo_device_mapping sdvo_mappings[2]; 873235783Skib /* indicate whether the LVDS_BORDER should be enabled or not */ 874235783Skib unsigned int lvds_border_bits; 875235783Skib /* Panel fitter placement and size for Ironlake+ */ 876235783Skib u32 pch_pf_pos, pch_pf_size; 877235783Skib 878235783Skib struct drm_crtc *plane_to_crtc_mapping[3]; 879235783Skib struct drm_crtc *pipe_to_crtc_mapping[3]; 880296548Sdumbbell wait_queue_head_t pending_flip_queue; 881235783Skib 882277487Skib struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 883296548Sdumbbell struct intel_ddi_plls ddi_plls; 884277487Skib 885235783Skib /* Reclocking support */ 886235783Skib bool render_reclock_avail; 887235783Skib bool lvds_downclock_avail; 888235783Skib /* indicates the reduced downclock for LVDS*/ 889235783Skib int lvds_downclock; 890235783Skib u16 orig_clock; 891235783Skib int child_dev_num; 892235783Skib struct child_device_config *child_dev; 893235783Skib 894235783Skib bool mchbar_need_disable; 895235783Skib 896296548Sdumbbell struct intel_l3_parity l3_parity; 897235783Skib 898296548Sdumbbell /* gen6+ rps state */ 899296548Sdumbbell struct intel_gen6_power_mgmt rps; 900235783Skib 901296548Sdumbbell /* ilk-only ips/rps state. Everything in here is protected by the global 902296548Sdumbbell * mchdev_lock in intel_pm.c */ 903296548Sdumbbell struct intel_ilk_power_mgmt ips; 904235783Skib 905235783Skib enum no_fbc_reason no_fbc_reason; 906235783Skib 907277487Skib struct drm_mm_node *compressed_fb; 908277487Skib struct drm_mm_node *compressed_llb; 909271705Sdumbbell 910296548Sdumbbell unsigned long last_gpu_reset; 911235783Skib 912296548Sdumbbell /* list of fbdev register on this device */ 913296548Sdumbbell struct intel_fbdev *fbdev; 914235783Skib 915296548Sdumbbell /* 916296548Sdumbbell * The console may be contended at resume, but we don't 917296548Sdumbbell * want it to block on it. 918296548Sdumbbell */ 919296548Sdumbbell struct task console_resume_work; 920235783Skib 921296548Sdumbbell struct backlight_device *backlight; 922235783Skib 923235783Skib struct drm_property *broadcast_rgb_property; 924235783Skib struct drm_property *force_audio_property; 925271705Sdumbbell 926271705Sdumbbell bool hw_contexts_disabled; 927271705Sdumbbell uint32_t hw_context_size; 928296548Sdumbbell 929296548Sdumbbell u32 fdi_rx_config; 930296548Sdumbbell 931296548Sdumbbell struct i915_suspend_saved_registers regfile; 932296548Sdumbbell 933296548Sdumbbell /* Old dri1 support infrastructure, beware the dragons ya fools entering 934296548Sdumbbell * here! */ 935296548Sdumbbell struct i915_dri1_state dri1; 936235783Skib} drm_i915_private_t; 937235783Skib 938271705Sdumbbell/* Iterate over initialised rings */ 939271705Sdumbbell#define for_each_ring(ring__, dev_priv__, i__) \ 940271705Sdumbbell for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 941296548Sdumbbell if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 942271705Sdumbbell 943235783Skibenum hdmi_force_audio { 944235783Skib HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 945235783Skib HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 946235783Skib HDMI_AUDIO_AUTO, /* trust EDID */ 947235783Skib HDMI_AUDIO_ON, /* force turn on HDMI audio */ 948235783Skib}; 949235783Skib 950235783Skibenum i915_cache_level { 951296548Sdumbbell I915_CACHE_NONE = 0, 952235783Skib I915_CACHE_LLC, 953296548Sdumbbell I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ 954235783Skib}; 955235783Skib 956296548Sdumbbellstruct drm_i915_gem_object_ops { 957296548Sdumbbell /* Interface between the GEM object and its backing storage. 958296548Sdumbbell * get_pages() is called once prior to the use of the associated set 959296548Sdumbbell * of pages before to binding them into the GTT, and put_pages() is 960296548Sdumbbell * called after we no longer need them. As we expect there to be 961296548Sdumbbell * associated cost with migrating pages between the backing storage 962296548Sdumbbell * and making them available for the GPU (e.g. clflush), we may hold 963296548Sdumbbell * onto the pages after they are no longer referenced by the GPU 964296548Sdumbbell * in case they may be used again shortly (for example migrating the 965296548Sdumbbell * pages to a different memory domain within the GTT). put_pages() 966296548Sdumbbell * will therefore most likely be called when the object itself is 967296548Sdumbbell * being released or under memory pressure (where we attempt to 968296548Sdumbbell * reap pages for the shrinker). 969296548Sdumbbell */ 970296548Sdumbbell int (*get_pages)(struct drm_i915_gem_object *); 971296548Sdumbbell void (*put_pages)(struct drm_i915_gem_object *); 972235783Skib}; 973235783Skib 974235783Skibstruct drm_i915_gem_object { 975235783Skib struct drm_gem_object base; 976235783Skib 977296548Sdumbbell const struct drm_i915_gem_object_ops *ops; 978296548Sdumbbell 979235783Skib /** Current space allocated to this object in the GTT, if any. */ 980235783Skib struct drm_mm_node *gtt_space; 981235783Skib struct list_head gtt_list; 982296548Sdumbbell 983296548Sdumbbell /** This object's place on the active/inactive lists */ 984235783Skib struct list_head ring_list; 985235783Skib struct list_head mm_list; 986235783Skib /** This object's place in the batchbuffer or on the eviction list */ 987235783Skib struct list_head exec_list; 988235783Skib 989235783Skib /** 990296548Sdumbbell * This is set if the object is on the active lists (has pending 991296548Sdumbbell * rendering and so a non-zero seqno), and is not set if it i s on 992296548Sdumbbell * inactive (ready to be unbound) list. 993235783Skib */ 994235783Skib unsigned int active:1; 995235783Skib 996235783Skib /** 997235783Skib * This is set if the object has been written to since last bound 998235783Skib * to the GTT 999235783Skib */ 1000235783Skib unsigned int dirty:1; 1001235783Skib 1002235783Skib /** 1003235783Skib * Fence register bits (if any) for this object. Will be set 1004235783Skib * as needed when mapped into the GTT. 1005235783Skib * Protected by dev->struct_mutex. 1006235783Skib */ 1007235783Skib signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1008235783Skib 1009235783Skib /** 1010235783Skib * Advice: are the backing pages purgeable? 1011235783Skib */ 1012235783Skib unsigned int madv:2; 1013235783Skib 1014235783Skib /** 1015235783Skib * Current tiling mode for the object. 1016235783Skib */ 1017235783Skib unsigned int tiling_mode:2; 1018277487Skib /** 1019277487Skib * Whether the tiling parameters for the currently associated fence 1020277487Skib * register have changed. Note that for the purposes of tracking 1021277487Skib * tiling changes we also treat the unfenced register, the register 1022277487Skib * slot that the object occupies whilst it executes a fenced 1023277487Skib * command (such as BLT on gen2/3), as a "fence". 1024277487Skib */ 1025277487Skib unsigned int fence_dirty:1; 1026235783Skib 1027235783Skib /** How many users have pinned this object in GTT space. The following 1028235783Skib * users can each hold at most one reference: pwrite/pread, pin_ioctl 1029235783Skib * (via user_pin_count), execbuffer (objects are not allowed multiple 1030235783Skib * times for the same batchbuffer), and the framebuffer code. When 1031235783Skib * switching/pageflipping, the framebuffer code has at most two buffers 1032235783Skib * pinned per crtc. 1033235783Skib * 1034235783Skib * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1035235783Skib * bits with absolutely no headroom. So use 4 bits. */ 1036235783Skib unsigned int pin_count:4; 1037235783Skib#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1038235783Skib 1039235783Skib /** 1040235783Skib * Is the object at the current location in the gtt mappable and 1041235783Skib * fenceable? Used to avoid costly recalculations. 1042235783Skib */ 1043235783Skib unsigned int map_and_fenceable:1; 1044235783Skib 1045235783Skib /** 1046235783Skib * Whether the current gtt mapping needs to be mappable (and isn't just 1047235783Skib * mappable by accident). Track pin and fault separate for a more 1048235783Skib * accurate mappable working set. 1049235783Skib */ 1050235783Skib unsigned int fault_mappable:1; 1051235783Skib unsigned int pin_mappable:1; 1052277487Skib unsigned int pin_display:1; 1053235783Skib 1054235783Skib /* 1055235783Skib * Is the GPU currently using a fence to access this buffer, 1056235783Skib */ 1057235783Skib unsigned int pending_fenced_gpu_access:1; 1058235783Skib unsigned int fenced_gpu_access:1; 1059235783Skib 1060235783Skib unsigned int cache_level:2; 1061235783Skib 1062235783Skib unsigned int has_aliasing_ppgtt_mapping:1; 1063271705Sdumbbell unsigned int has_global_gtt_mapping:1; 1064296548Sdumbbell unsigned int has_dma_mapping:1; 1065235783Skib 1066235783Skib vm_page_t *pages; 1067277487Skib int pages_pin_count; 1068235783Skib 1069235783Skib /** 1070235783Skib * Used for performing relocations during execbuffer insertion. 1071235783Skib */ 1072296548Sdumbbell struct hlist_node exec_node; 1073235783Skib unsigned long exec_handle; 1074235783Skib struct drm_i915_gem_exec_object2 *exec_entry; 1075235783Skib 1076235783Skib /** 1077235783Skib * Current offset of the object in GTT space. 1078235783Skib * 1079235783Skib * This is the same as gtt_space->start 1080235783Skib */ 1081235783Skib uint32_t gtt_offset; 1082235783Skib 1083277487Skib struct intel_ring_buffer *ring; 1084277487Skib 1085235783Skib /** Breadcrumb of last rendering to the buffer. */ 1086296548Sdumbbell uint32_t last_read_seqno; 1087296548Sdumbbell uint32_t last_write_seqno; 1088235783Skib /** Breadcrumb of last fenced GPU access to the buffer. */ 1089235783Skib uint32_t last_fenced_seqno; 1090235783Skib 1091235783Skib /** Current tiling stride for the object, if it's tiled. */ 1092235783Skib uint32_t stride; 1093235783Skib 1094235783Skib /** Record of address bit 17 of each page at last unbind. */ 1095235783Skib unsigned long *bit_17; 1096235783Skib 1097235783Skib /** User space pin count and filp owning the pin */ 1098235783Skib uint32_t user_pin_count; 1099235783Skib struct drm_file *pin_filp; 1100235783Skib 1101235783Skib /** for phy allocated objects */ 1102235783Skib struct drm_i915_gem_phys_object *phys_obj; 1103235783Skib 1104235783Skib /** 1105235783Skib * Number of crtcs where this object is currently the fb, but 1106235783Skib * will be page flipped away on the next vblank. When it 1107235783Skib * reaches 0, dev_priv->pending_flip_queue will be woken up. 1108235783Skib */ 1109296548Sdumbbell atomic_t pending_flip; 1110235783Skib}; 1111296548Sdumbbell#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1112235783Skib 1113296548Sdumbbell#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1114235783Skib 1115235783Skib/** 1116235783Skib * Request queue structure. 1117235783Skib * 1118235783Skib * The request queue allows us to note sequence numbers that have been emitted 1119235783Skib * and may be associated with active buffers to be retired. 1120235783Skib * 1121235783Skib * By keeping this list, we can avoid having to do questionable 1122235783Skib * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1123235783Skib * an emission time with seqnos for tracking how far ahead of the GPU we are. 1124235783Skib */ 1125235783Skibstruct drm_i915_gem_request { 1126235783Skib /** On Which ring this request was generated */ 1127235783Skib struct intel_ring_buffer *ring; 1128235783Skib 1129235783Skib /** GEM sequence number associated with this request. */ 1130235783Skib uint32_t seqno; 1131235783Skib 1132298955Spfg /** Position in the ringbuffer of the end of the request */ 1133235783Skib u32 tail; 1134235783Skib 1135235783Skib /** Time at which this request was emitted, in jiffies. */ 1136235783Skib unsigned long emitted_jiffies; 1137235783Skib 1138235783Skib /** global list entry for this request */ 1139235783Skib struct list_head list; 1140235783Skib 1141235783Skib struct drm_i915_file_private *file_priv; 1142235783Skib /** file_priv list entry for this request */ 1143235783Skib struct list_head client_list; 1144235783Skib}; 1145235783Skib 1146235783Skibstruct drm_i915_file_private { 1147235783Skib struct { 1148296548Sdumbbell struct mtx lock; 1149235783Skib struct list_head request_list; 1150235783Skib } mm; 1151271705Sdumbbell struct drm_gem_names context_idr; 1152235783Skib}; 1153235783Skib 1154296548Sdumbbell#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1155235783Skib 1156296548Sdumbbell#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1157296548Sdumbbell#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1158296548Sdumbbell#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1159296548Sdumbbell#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1160296548Sdumbbell#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1161296548Sdumbbell#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1162296548Sdumbbell#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1163296548Sdumbbell#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1164296548Sdumbbell#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1165296548Sdumbbell#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1166296548Sdumbbell#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1167296548Sdumbbell#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1168296548Sdumbbell#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1169296548Sdumbbell#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1170296548Sdumbbell#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1171296548Sdumbbell#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1172296548Sdumbbell#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1173296548Sdumbbell#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1174296548Sdumbbell#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1175296548Sdumbbell#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1176296548Sdumbbell (dev)->pci_device == 0x0152 || \ 1177296548Sdumbbell (dev)->pci_device == 0x015a) 1178296548Sdumbbell#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1179296548Sdumbbell (dev)->pci_device == 0x0106 || \ 1180296548Sdumbbell (dev)->pci_device == 0x010A) 1181296548Sdumbbell#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1182296548Sdumbbell#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1183296548Sdumbbell#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1184296548Sdumbbell#define IS_ULT(dev) (IS_HASWELL(dev) && \ 1185296548Sdumbbell ((dev)->pci_device & 0xFF00) == 0x0A00) 1186296548Sdumbbell 1187296548Sdumbbell/* 1188296548Sdumbbell * The genX designation typically refers to the render engine, so render 1189296548Sdumbbell * capability related checks should use IS_GEN, while display and other checks 1190296548Sdumbbell * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1191296548Sdumbbell * chips, etc.). 1192296548Sdumbbell */ 1193296548Sdumbbell#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1194296548Sdumbbell#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1195296548Sdumbbell#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1196296548Sdumbbell#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1197296548Sdumbbell#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1198296548Sdumbbell#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1199296548Sdumbbell 1200296548Sdumbbell#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1201296548Sdumbbell#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1202296548Sdumbbell#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1203296548Sdumbbell#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1204296548Sdumbbell 1205296548Sdumbbell#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1206296548Sdumbbell#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1207296548Sdumbbell 1208296548Sdumbbell#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1209296548Sdumbbell#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1210296548Sdumbbell 1211296548Sdumbbell/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1212296548Sdumbbell#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1213296548Sdumbbell 1214296548Sdumbbell/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1215296548Sdumbbell * rows, which changed the alignment requirements and fence programming. 1216296548Sdumbbell */ 1217296548Sdumbbell#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1218296548Sdumbbell IS_I915GM(dev))) 1219296548Sdumbbell#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1220296548Sdumbbell#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1221296548Sdumbbell#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1222296548Sdumbbell#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1223296548Sdumbbell#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1224296548Sdumbbell#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1225296548Sdumbbell/* dsparb controlled by hw only */ 1226296548Sdumbbell#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1227296548Sdumbbell 1228296548Sdumbbell#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1229296548Sdumbbell#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1230296548Sdumbbell#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1231296548Sdumbbell 1232296548Sdumbbell#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1233296548Sdumbbell 1234296548Sdumbbell#define INTEL_PCH_DEVICE_ID_MASK 0xff00 1235296548Sdumbbell#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1236296548Sdumbbell#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1237296548Sdumbbell#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1238296548Sdumbbell#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1239296548Sdumbbell#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1240296548Sdumbbell 1241296548Sdumbbell#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1242296548Sdumbbell#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1243296548Sdumbbell#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1244296548Sdumbbell#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1245296548Sdumbbell#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1246296548Sdumbbell 1247296548Sdumbbell#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1248296548Sdumbbell 1249296548Sdumbbell#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1250296548Sdumbbell 1251296548Sdumbbell#define GT_FREQUENCY_MULTIPLIER 50 1252296548Sdumbbell 1253235783Skib/** 1254235783Skib * RC6 is a special power stage which allows the GPU to enter an very 1255235783Skib * low-voltage mode when idle, using down to 0V while at this stage. This 1256235783Skib * stage is entered automatically when the GPU is idle when RC6 support is 1257235783Skib * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1258235783Skib * 1259235783Skib * There are different RC6 modes available in Intel GPU, which differentiate 1260235783Skib * among each other with the latency required to enter and leave RC6 and 1261235783Skib * voltage consumed by the GPU in different states. 1262235783Skib * 1263235783Skib * The combination of the following flags define which states GPU is allowed 1264235783Skib * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1265235783Skib * RC6pp is deepest RC6. Their support by hardware varies according to the 1266235783Skib * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1267235783Skib * which brings the most power savings; deeper states save more power, but 1268235783Skib * require higher latency to switch to and wake up. 1269235783Skib */ 1270235783Skib#define INTEL_RC6_ENABLE (1<<0) 1271235783Skib#define INTEL_RC6p_ENABLE (1<<1) 1272235783Skib#define INTEL_RC6pp_ENABLE (1<<2) 1273235783Skib 1274235783Skibextern struct drm_ioctl_desc i915_ioctls[]; 1275296548Sdumbbellextern int i915_max_ioctl; 1276296548Sdumbbellextern unsigned int i915_fbpercrtc __always_unused; 1277296548Sdumbbellextern int i915_panel_ignore_lid __read_mostly; 1278296548Sdumbbellextern unsigned int i915_powersave __read_mostly; 1279296548Sdumbbellextern int i915_semaphores __read_mostly; 1280296548Sdumbbellextern unsigned int i915_lvds_downclock __read_mostly; 1281296548Sdumbbellextern int i915_lvds_channel_mode __read_mostly; 1282296548Sdumbbellextern int i915_panel_use_ssc __read_mostly; 1283296548Sdumbbellextern int i915_vbt_sdvo_panel_type __read_mostly; 1284296548Sdumbbellextern int i915_enable_rc6 __read_mostly; 1285296548Sdumbbellextern int i915_enable_fbc __read_mostly; 1286296548Sdumbbellextern int i915_enable_hangcheck __read_mostly; 1287296548Sdumbbellextern int i915_enable_ppgtt __read_mostly; 1288296548Sdumbbellextern unsigned int i915_preliminary_hw_support __read_mostly; 1289296548Sdumbbell 1290280183Sdumbbellextern struct drm_driver i915_driver_info; 1291235783Skibextern struct cdev_pager_ops i915_gem_pager_ops; 1292296548Sdumbbellextern int intel_iommu_gfx_mapped; 1293235783Skib 1294235783Skibconst struct intel_device_info *i915_get_device_id(int device); 1295235783Skib 1296235783Skib/* i915_debug.c */ 1297235783Skibint i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1298235783Skib struct sysctl_oid *top); 1299235783Skibvoid i915_sysctl_cleanup(struct drm_device *dev); 1300235783Skib 1301296548Sdumbbellextern int i915_suspend(struct drm_device *dev, pm_message_t state); 1302296548Sdumbbellextern int i915_resume(struct drm_device *dev); 1303280183Sdumbbellextern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1304280183Sdumbbellextern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1305280183Sdumbbell 1306235783Skib /* i915_dma.c */ 1307277487Skibvoid i915_update_dri1_breadcrumb(struct drm_device *dev); 1308235783Skibextern void i915_kernel_lost_context(struct drm_device * dev); 1309235783Skibextern int i915_driver_load(struct drm_device *, unsigned long flags); 1310235783Skibextern int i915_driver_unload(struct drm_device *); 1311235783Skibextern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1312235783Skibextern void i915_driver_lastclose(struct drm_device * dev); 1313235783Skibextern void i915_driver_preclose(struct drm_device *dev, 1314235783Skib struct drm_file *file_priv); 1315235783Skibextern void i915_driver_postclose(struct drm_device *dev, 1316235783Skib struct drm_file *file_priv); 1317235783Skibextern int i915_driver_device_is_agp(struct drm_device * dev); 1318296548Sdumbbell#ifdef CONFIG_COMPAT 1319235783Skibextern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1320235783Skib unsigned long arg); 1321296548Sdumbbell#endif 1322235783Skibextern int i915_emit_box(struct drm_device *dev, 1323287177Sbapt struct drm_clip_rect *box, 1324287177Sbapt int DR1, int DR4); 1325296548Sdumbbellextern int intel_gpu_reset(struct drm_device *dev); 1326296548Sdumbbellextern int i915_reset(struct drm_device *dev); 1327296548Sdumbbellextern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1328296548Sdumbbellextern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1329296548Sdumbbellextern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1330296548Sdumbbellextern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1331235783Skib 1332296548Sdumbbellextern int i915_batchbuffer(struct drm_device *dev, void *data, 1333296548Sdumbbell struct drm_file *file_priv); 1334296548Sdumbbellextern int i915_cmdbuffer(struct drm_device *dev, void *data, 1335296548Sdumbbell struct drm_file *file_priv); 1336235783Skibextern int i915_irq_emit(struct drm_device *dev, void *data, 1337235783Skib struct drm_file *file_priv); 1338296548Sdumbbellextern int i915_getparam(struct drm_device *dev, void *data, 1339296548Sdumbbell struct drm_file *file_priv); 1340296548Sdumbbell 1341296548Sdumbbellextern void intel_console_resume(void *context, int pending); 1342296548Sdumbbell 1343296548Sdumbbell/* i915_irq.c */ 1344296548Sdumbbellvoid i915_hangcheck_elapsed(void *data); 1345296548Sdumbbellvoid i915_handle_error(struct drm_device *dev, bool wedged); 1346296548Sdumbbell 1347235783Skibextern void intel_irq_init(struct drm_device *dev); 1348296548Sdumbbellextern void intel_gt_init(struct drm_device *dev); 1349296548Sdumbbellextern void intel_gt_reset(struct drm_device *dev); 1350235783Skib 1351277487Skibvoid i915_error_state_free(struct drm_i915_error_state *error); 1352235783Skib 1353296548Sdumbbellvoid 1354296548Sdumbbelli915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1355235783Skib 1356296548Sdumbbellvoid 1357296548Sdumbbelli915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1358235783Skib 1359296548Sdumbbellvoid intel_enable_asle(struct drm_device *dev); 1360296548Sdumbbell 1361296548Sdumbbell//#ifdef CONFIG_DEBUG_FS 1362296548Sdumbbellextern void i915_destroy_error_state(struct drm_device *dev); 1363296548Sdumbbell//#else 1364296548Sdumbbell//#define i915_destroy_error_state(x) 1365296548Sdumbbell//#endif 1366296548Sdumbbell 1367235783Skib/* i915_gem.c */ 1368235783Skibint i915_gem_init_ioctl(struct drm_device *dev, void *data, 1369235783Skib struct drm_file *file_priv); 1370235783Skibint i915_gem_create_ioctl(struct drm_device *dev, void *data, 1371235783Skib struct drm_file *file_priv); 1372235783Skibint i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1373235783Skib struct drm_file *file_priv); 1374235783Skibint i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1375235783Skib struct drm_file *file_priv); 1376235783Skibint i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1377235783Skib struct drm_file *file_priv); 1378235783Skibint i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1379235783Skib struct drm_file *file_priv); 1380235783Skibint i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1381235783Skib struct drm_file *file_priv); 1382235783Skibint i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1383235783Skib struct drm_file *file_priv); 1384235783Skibint i915_gem_execbuffer(struct drm_device *dev, void *data, 1385235783Skib struct drm_file *file_priv); 1386235783Skibint i915_gem_execbuffer2(struct drm_device *dev, void *data, 1387296548Sdumbbell struct drm_file *file_priv); 1388235783Skibint i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1389235783Skib struct drm_file *file_priv); 1390235783Skibint i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1391235783Skib struct drm_file *file_priv); 1392235783Skibint i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1393235783Skib struct drm_file *file_priv); 1394296548Sdumbbellint i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1395296548Sdumbbell struct drm_file *file); 1396296548Sdumbbellint i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1397296548Sdumbbell struct drm_file *file); 1398235783Skibint i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1399235783Skib struct drm_file *file_priv); 1400235783Skibint i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1401235783Skib struct drm_file *file_priv); 1402235783Skibint i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1403235783Skib struct drm_file *file_priv); 1404235783Skibint i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1405235783Skib struct drm_file *file_priv); 1406235783Skibint i915_gem_set_tiling(struct drm_device *dev, void *data, 1407235783Skib struct drm_file *file_priv); 1408235783Skibint i915_gem_get_tiling(struct drm_device *dev, void *data, 1409235783Skib struct drm_file *file_priv); 1410235783Skibint i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1411235783Skib struct drm_file *file_priv); 1412296548Sdumbbellint i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1413296548Sdumbbell struct drm_file *file_priv); 1414235783Skibvoid i915_gem_load(struct drm_device *dev); 1415235783Skibint i915_gem_init_object(struct drm_gem_object *obj); 1416296548Sdumbbellvoid i915_gem_object_init(struct drm_i915_gem_object *obj, 1417296548Sdumbbell const struct drm_i915_gem_object_ops *ops); 1418296548Sdumbbellstruct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1419296548Sdumbbell size_t size); 1420235783Skibvoid i915_gem_free_object(struct drm_gem_object *obj); 1421296548Sdumbbellint __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1422296548Sdumbbell uint32_t alignment, 1423296548Sdumbbell bool map_and_fenceable, 1424296548Sdumbbell bool nonblocking); 1425235783Skibvoid i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1426296548Sdumbbellint __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1427296548Sdumbbellvoid i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1428235783Skibvoid i915_gem_lastclose(struct drm_device *dev); 1429296548Sdumbbell 1430296548Sdumbbellint __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1431235783Skibuint32_t i915_get_gem_seqno(struct drm_device *dev); 1432296548Sdumbbellstatic inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1433296548Sdumbbell{ 1434296548Sdumbbell /* KASSERT(obj->pages != NULL, ("pin and NULL pages")); */ 1435296548Sdumbbell obj->pages_pin_count++; 1436296548Sdumbbell} 1437235783Skib 1438296548Sdumbbellstatic inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1439296548Sdumbbell{ 1440296548Sdumbbell KASSERT(obj->pages_pin_count != 0, ("zero pages_pin_count")); 1441296548Sdumbbell obj->pages_pin_count--; 1442296548Sdumbbell} 1443296548Sdumbbell 1444296548Sdumbbellint __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1445296548Sdumbbellint i915_gem_object_sync(struct drm_i915_gem_object *obj, 1446296548Sdumbbell struct intel_ring_buffer *to); 1447296548Sdumbbellvoid i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1448296548Sdumbbell struct intel_ring_buffer *ring); 1449296548Sdumbbell 1450296548Sdumbbellint i915_gem_dumb_create(struct drm_file *file_priv, 1451296548Sdumbbell struct drm_device *dev, 1452296548Sdumbbell struct drm_mode_create_dumb *args); 1453296548Sdumbbellint i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1454296548Sdumbbell uint32_t handle, uint64_t *offset); 1455296548Sdumbbellint i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1456296548Sdumbbell uint32_t handle); 1457296548Sdumbbell/** 1458296548Sdumbbell * Returns true if seq1 is later than seq2. 1459296548Sdumbbell */ 1460277487Skibstatic inline bool 1461296548Sdumbbelli915_seqno_passed(uint32_t seq1, uint32_t seq2) 1462296548Sdumbbell{ 1463296548Sdumbbell return (int32_t)(seq1 - seq2) >= 0; 1464296548Sdumbbell} 1465296548Sdumbbell 1466296548Sdumbbellextern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1467296548Sdumbbell 1468296548Sdumbbellint __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1469296548Sdumbbellint __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1470296548Sdumbbell 1471296548Sdumbbellstatic inline bool 1472235783Skibi915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1473235783Skib{ 1474235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1475235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1476235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count++; 1477277487Skib return true; 1478277487Skib } else 1479277487Skib return false; 1480235783Skib} 1481235783Skib 1482235783Skibstatic inline void 1483235783Skibi915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1484235783Skib{ 1485235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1486235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1487235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count--; 1488235783Skib } 1489235783Skib} 1490235783Skib 1491235783Skibvoid i915_gem_retire_requests(struct drm_device *dev); 1492235783Skibvoid i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1493296548Sdumbbellint __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1494296548Sdumbbell bool interruptible); 1495296548Sdumbbell 1496296548Sdumbbellvoid i915_gem_reset(struct drm_device *dev); 1497235783Skibvoid i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1498296548Sdumbbellint __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1499296548Sdumbbell uint32_t read_domains, 1500296548Sdumbbell uint32_t write_domain); 1501296548Sdumbbellint __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1502296548Sdumbbellint __must_check i915_gem_init(struct drm_device *dev); 1503296548Sdumbbellint __must_check i915_gem_init_hw(struct drm_device *dev); 1504296548Sdumbbellvoid i915_gem_l3_remap(struct drm_device *dev); 1505235783Skibvoid i915_gem_init_swizzling(struct drm_device *dev); 1506235783Skibvoid i915_gem_init_ppgtt(struct drm_device *dev); 1507235783Skibvoid i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1508296548Sdumbbellint __must_check i915_gpu_idle(struct drm_device *dev); 1509296548Sdumbbellint __must_check i915_gem_idle(struct drm_device *dev); 1510296548Sdumbbellint i915_add_request(struct intel_ring_buffer *ring, 1511296548Sdumbbell struct drm_file *file, 1512296548Sdumbbell u32 *seqno); 1513296548Sdumbbellint __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1514296548Sdumbbell uint32_t seqno); 1515235783Skibint i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1516235783Skib uint64_t *phys); 1517296548Sdumbbellint __must_check 1518296548Sdumbbelli915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1519296548Sdumbbell bool write); 1520296548Sdumbbellint __must_check 1521296548Sdumbbelli915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1522296548Sdumbbellint __must_check 1523296548Sdumbbelli915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1524296548Sdumbbell u32 alignment, 1525296548Sdumbbell struct intel_ring_buffer *pipelined); 1526296548Sdumbbellvoid i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 1527296548Sdumbbellint i915_gem_attach_phys_object(struct drm_device *dev, 1528296548Sdumbbell struct drm_i915_gem_object *obj, 1529296548Sdumbbell int id, 1530296548Sdumbbell int align); 1531296548Sdumbbellvoid i915_gem_detach_phys_object(struct drm_device *dev, 1532296548Sdumbbell struct drm_i915_gem_object *obj); 1533296548Sdumbbellvoid i915_gem_free_all_phys_object(struct drm_device *dev); 1534235783Skibvoid i915_gem_release(struct drm_device *dev, struct drm_file *file); 1535296548Sdumbbell 1536296548Sdumbbelluint32_t 1537296548Sdumbbelli915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1538296548Sdumbbell uint32_t size, 1539296548Sdumbbell int tiling_mode); 1540296548Sdumbbell 1541235783Skibint i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1542296548Sdumbbell enum i915_cache_level cache_level); 1543235783Skib 1544296548Sdumbbell#ifdef FREEBSD_WIP 1545296548Sdumbbellstruct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1546296548Sdumbbell struct dma_buf *dma_buf); 1547296548Sdumbbell 1548296548Sdumbbellstruct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1549296548Sdumbbell struct drm_gem_object *gem_obj, int flags); 1550296548Sdumbbell#endif /* FREEBSD_WIP */ 1551296548Sdumbbell 1552296548Sdumbbellint i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1553296548Sdumbbell 1554271705Sdumbbell/* i915_gem_context.c */ 1555271705Sdumbbellvoid i915_gem_context_init(struct drm_device *dev); 1556271705Sdumbbellvoid i915_gem_context_fini(struct drm_device *dev); 1557271705Sdumbbellvoid i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1558271705Sdumbbellint i915_switch_context(struct intel_ring_buffer *ring, 1559271705Sdumbbell struct drm_file *file, int to_id); 1560271705Sdumbbellint i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1561271705Sdumbbell struct drm_file *file); 1562271705Sdumbbellint i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1563271705Sdumbbell struct drm_file *file); 1564271705Sdumbbell 1565296548Sdumbbell/* i915_gem_gtt.c */ 1566296548Sdumbbellint __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1567296548Sdumbbellvoid i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1568296548Sdumbbellvoid i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1569296548Sdumbbell struct drm_i915_gem_object *obj, 1570296548Sdumbbell enum i915_cache_level cache_level); 1571296548Sdumbbellvoid i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1572296548Sdumbbell struct drm_i915_gem_object *obj); 1573235783Skib 1574296548Sdumbbellvoid i915_gem_restore_gtt_mappings(struct drm_device *dev); 1575296548Sdumbbellint __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1576296548Sdumbbellvoid i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1577296548Sdumbbell enum i915_cache_level cache_level); 1578296548Sdumbbellvoid i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1579296548Sdumbbellvoid i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1580296548Sdumbbellvoid i915_gem_init_global_gtt(struct drm_device *dev, 1581296548Sdumbbell unsigned long start, 1582296548Sdumbbell unsigned long mappable_end, 1583296548Sdumbbell unsigned long end); 1584296548Sdumbbellint i915_gem_gtt_init(struct drm_device *dev); 1585296548Sdumbbellvoid i915_gem_gtt_fini(struct drm_device *dev); 1586296548Sdumbbellstatic inline void i915_gem_chipset_flush(struct drm_device *dev) 1587296548Sdumbbell{ 1588296548Sdumbbell if (INTEL_INFO(dev)->gen < 6) 1589296548Sdumbbell intel_gtt_chipset_flush(); 1590296548Sdumbbell} 1591235783Skib 1592296548Sdumbbell/* i915_gem_evict.c */ 1593296548Sdumbbellint __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1594296548Sdumbbell unsigned alignment, 1595296548Sdumbbell unsigned cache_level, 1596296548Sdumbbell bool mappable, 1597296548Sdumbbell bool nonblock); 1598296548Sdumbbellint i915_gem_evict_everything(struct drm_device *dev); 1599296548Sdumbbell 1600296548Sdumbbell/* i915_gem_stolen.c */ 1601296548Sdumbbellint i915_gem_init_stolen(struct drm_device *dev); 1602296548Sdumbbellvoid i915_gem_cleanup_stolen(struct drm_device *dev); 1603296548Sdumbbell 1604235783Skib/* i915_gem_tiling.c */ 1605235783Skibvoid i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1606235783Skibvoid i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1607235783Skibvoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1608277487Skibvoid i915_gem_object_do_bit_17_swizzle_page(struct drm_i915_gem_object *obj, 1609277487Skib struct vm_page *m); 1610235783Skib 1611296548Sdumbbell/* i915_gem_debug.c */ 1612296548Sdumbbellvoid i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1613296548Sdumbbell const char *where, uint32_t mark); 1614296548Sdumbbell#if WATCH_LISTS 1615296548Sdumbbellint i915_verify_lists(struct drm_device *dev); 1616296548Sdumbbell#else 1617296548Sdumbbell#define i915_verify_lists(dev) 0 1618296548Sdumbbell#endif 1619296548Sdumbbellvoid i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1620296548Sdumbbell int handle); 1621235783Skib 1622235783Skib/* i915_suspend.c */ 1623235783Skibextern int i915_save_state(struct drm_device *dev); 1624235783Skibextern int i915_restore_state(struct drm_device *dev); 1625235783Skib 1626296548Sdumbbell/* intel_i2c.c */ 1627235783Skibextern int intel_setup_gmbus(struct drm_device *dev); 1628235783Skibextern void intel_teardown_gmbus(struct drm_device *dev); 1629277487Skibstatic inline bool intel_gmbus_is_port_valid(unsigned port) 1630277487Skib{ 1631277487Skib return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1632277487Skib} 1633235783Skib 1634296548Sdumbbellextern device_t intel_gmbus_get_adapter( 1635296548Sdumbbell struct drm_i915_private *dev_priv, unsigned port); 1636296548Sdumbbellextern void intel_gmbus_set_speed(device_t idev, int speed); 1637296548Sdumbbellextern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1638296548Sdumbbellextern bool intel_gmbus_is_forced_bit(device_t adapter); 1639296548Sdumbbellextern void intel_i2c_reset(struct drm_device *dev); 1640296548Sdumbbell 1641235783Skib/* intel_opregion.c */ 1642296548Sdumbbellextern int intel_opregion_setup(struct drm_device *dev); 1643296548Sdumbbell#ifdef CONFIG_ACPI 1644270516Sadrianextern void intel_opregion_init(struct drm_device *dev); 1645235783Skibextern void intel_opregion_fini(struct drm_device *dev); 1646270516Sadrianextern void intel_opregion_asle_intr(struct drm_device *dev); 1647270516Sadrianextern void intel_opregion_gse_intr(struct drm_device *dev); 1648270516Sadrianextern void intel_opregion_enable_asle(struct drm_device *dev); 1649296548Sdumbbell#else 1650296548Sdumbbellstatic inline void intel_opregion_init(struct drm_device *dev) { return; } 1651296548Sdumbbellstatic inline void intel_opregion_fini(struct drm_device *dev) { return; } 1652296548Sdumbbellstatic inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1653296548Sdumbbellstatic inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1654296548Sdumbbellstatic inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1655296548Sdumbbell#endif 1656235783Skib 1657296548Sdumbbell/* intel_acpi.c */ 1658296548Sdumbbell#ifdef CONFIG_ACPI 1659296548Sdumbbellextern void intel_register_dsm_handler(void); 1660296548Sdumbbellextern void intel_unregister_dsm_handler(void); 1661296548Sdumbbell#else 1662296548Sdumbbellstatic inline void intel_register_dsm_handler(void) { return; } 1663296548Sdumbbellstatic inline void intel_unregister_dsm_handler(void) { return; } 1664296548Sdumbbell#endif /* CONFIG_ACPI */ 1665235783Skib 1666235783Skib/* modesetting */ 1667277487Skibextern void intel_modeset_init_hw(struct drm_device *dev); 1668235783Skibextern void intel_modeset_init(struct drm_device *dev); 1669235783Skibextern void intel_modeset_gem_init(struct drm_device *dev); 1670235783Skibextern void intel_modeset_cleanup(struct drm_device *dev); 1671235783Skibextern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1672296548Sdumbbellextern void intel_modeset_setup_hw_state(struct drm_device *dev, 1673296548Sdumbbell bool force_restore); 1674235783Skibextern void intel_disable_fbc(struct drm_device *dev); 1675235783Skibextern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1676296548Sdumbbellextern void intel_init_pch_refclk(struct drm_device *dev); 1677235783Skibextern void gen6_set_rps(struct drm_device *dev, u8 val); 1678235783Skibextern void intel_detect_pch(struct drm_device *dev); 1679235783Skibextern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1680296548Sdumbbellextern int intel_enable_rc6(const struct drm_device *dev); 1681235783Skib 1682277487Skibextern bool i915_semaphore_is_enabled(struct drm_device *dev); 1683296548Sdumbbellint i915_reg_read_ioctl(struct drm_device *dev, void *data, 1684296548Sdumbbell struct drm_file *file); 1685235783Skib 1686296548Sdumbbell/* overlay */ 1687296548Sdumbbell//#ifdef CONFIG_DEBUG_FS 1688296548Sdumbbellextern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1689296548Sdumbbellextern void intel_overlay_print_error_state(struct sbuf *m, struct intel_overlay_error_state *error); 1690277487Skib 1691296548Sdumbbellextern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1692235783Skibextern void intel_display_print_error_state(struct sbuf *m, 1693296548Sdumbbell struct drm_device *dev, 1694296548Sdumbbell struct intel_display_error_state *error); 1695296548Sdumbbell//#endif 1696235783Skib 1697235783Skibstatic inline void 1698235783Skibtrace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1699235783Skib{ 1700235783Skib 1701235783Skib CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val); 1702235783Skib} 1703235783Skib 1704235783Skib/* On SNB platform, before reading ring registers forcewake bit 1705235783Skib * must be set to prevent GT core from power down and stale values being 1706235783Skib * returned. 1707235783Skib */ 1708235783Skibvoid gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1709235783Skibvoid gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1710235783Skibint __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1711235783Skib 1712296548Sdumbbellint sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1713296548Sdumbbellint sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1714296548Sdumbbell 1715235783Skib#define __i915_read(x, y) \ 1716235783Skib u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1717235783Skib 1718235783Skib__i915_read(8, 8) 1719235783Skib__i915_read(16, 16) 1720235783Skib__i915_read(32, 32) 1721235783Skib__i915_read(64, 64) 1722235783Skib#undef __i915_read 1723235783Skib 1724235783Skib#define __i915_write(x, y) \ 1725235783Skib void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1726235783Skib 1727235783Skib__i915_write(8, 8) 1728235783Skib__i915_write(16, 16) 1729235783Skib__i915_write(32, 32) 1730235783Skib__i915_write(64, 64) 1731235783Skib#undef __i915_write 1732235783Skib 1733235783Skib#define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1734235783Skib#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1735235783Skib 1736235783Skib#define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1737235783Skib#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1738235783Skib#define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1739235783Skib#define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1740235783Skib 1741235783Skib#define I915_READ(reg) i915_read32(dev_priv, (reg)) 1742235783Skib#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1743235783Skib#define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1744235783Skib#define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1745235783Skib 1746235783Skib#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1747235783Skib#define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1748235783Skib 1749235783Skib#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1750235783Skib#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1751235783Skib 1752235783Skibu32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1753235783Skib 1754235783Skib#endif 1755