1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/dev/drm2/i915/intel_iic.c 349227 2019-06-20 09:23:03Z avg $"); 31 32#include <dev/drm2/drmP.h> 33#include <dev/drm2/i915/intel_drv.h> 34#include <dev/drm2/i915/i915_drm.h> 35#include <dev/drm2/i915/i915_drv.h> 36#include <dev/iicbus/iic.h> 37#include <dev/iicbus/iiconf.h> 38#include <dev/iicbus/iicbus.h> 39#include "iicbus_if.h" 40#include "iicbb_if.h" 41 42struct gmbus_port { 43 const char *name; 44 int reg; 45}; 46 47static const struct gmbus_port gmbus_ports[] = { 48 { "ssc", GPIOB }, 49 { "vga", GPIOA }, 50 { "panel", GPIOC }, 51 { "dpc", GPIOD }, 52 { "dpb", GPIOE }, 53 { "dpd", GPIOF }, 54}; 55 56/* Intel GPIO access functions */ 57 58#define I2C_RISEFALL_TIME 10 59 60/* 61 * FIXME Linux<->FreeBSD: dvo_ns2501.C wants the struct intel_gmbus 62 * below but it just has the device_t at hand. It still uses 63 * device_get_softc(), thus expects struct intel_gmbus to remain the 64 * first member. 65 */ 66struct intel_iic_softc { 67 struct intel_gmbus *bus; 68 device_t iic_dev; 69 char name[32]; 70}; 71 72static inline struct intel_gmbus * 73to_intel_gmbus(device_t i2c) 74{ 75 struct intel_iic_softc *sc; 76 77 sc = device_get_softc(i2c); 78 return sc->bus; 79} 80 81bool intel_gmbus_is_forced_bit(device_t adapter) 82{ 83 struct intel_iic_softc *sc = device_get_softc(adapter); 84 struct intel_gmbus *bus = sc->bus; 85 86 return bus->force_bit; 87} 88 89void 90intel_i2c_reset(struct drm_device *dev) 91{ 92 struct drm_i915_private *dev_priv = dev->dev_private; 93 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 94} 95 96static int 97intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 98{ 99 struct intel_iic_softc *sc; 100 struct drm_device *dev; 101 102 sc = device_get_softc(idev); 103 dev = sc->bus->dev_priv->dev; 104 105 intel_i2c_reset(dev); 106 return (0); 107} 108 109static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 110{ 111 u32 val; 112 113 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 114 if (!IS_PINEVIEW(dev_priv->dev)) 115 return; 116 117 val = I915_READ(DSPCLK_GATE_D); 118 if (enable) 119 val |= DPCUNIT_CLOCK_GATE_DISABLE; 120 else 121 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 122 I915_WRITE(DSPCLK_GATE_D, val); 123} 124 125static u32 get_reserved(struct intel_gmbus *bus) 126{ 127 struct drm_i915_private *dev_priv = bus->dev_priv; 128 struct drm_device *dev = dev_priv->dev; 129 u32 reserved = 0; 130 131 /* On most chips, these bits must be preserved in software. */ 132 if (!IS_I830(dev) && !IS_845G(dev)) 133 reserved = I915_READ_NOTRACE(bus->gpio_reg) & 134 (GPIO_DATA_PULLUP_DISABLE | 135 GPIO_CLOCK_PULLUP_DISABLE); 136 137 return reserved; 138} 139 140static int get_clock(device_t adapter) 141{ 142 struct intel_iic_softc *sc = device_get_softc(adapter); 143 struct intel_gmbus *bus = sc->bus; 144 struct drm_i915_private *dev_priv = bus->dev_priv; 145 u32 reserved = get_reserved(bus); 146 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 147 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 148 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 149} 150 151static int get_data(device_t adapter) 152{ 153 struct intel_iic_softc *sc = device_get_softc(adapter); 154 struct intel_gmbus *bus = sc->bus; 155 struct drm_i915_private *dev_priv = bus->dev_priv; 156 u32 reserved = get_reserved(bus); 157 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 158 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 159 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 160} 161 162static void set_clock(device_t adapter, int state_high) 163{ 164 struct intel_iic_softc *sc = device_get_softc(adapter); 165 struct intel_gmbus *bus = sc->bus; 166 struct drm_i915_private *dev_priv = bus->dev_priv; 167 u32 reserved = get_reserved(bus); 168 u32 clock_bits; 169 170 if (state_high) 171 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 172 else 173 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 174 GPIO_CLOCK_VAL_MASK; 175 176 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); 177 POSTING_READ(bus->gpio_reg); 178} 179 180static void set_data(device_t adapter, int state_high) 181{ 182 struct intel_iic_softc *sc = device_get_softc(adapter); 183 struct intel_gmbus *bus = sc->bus; 184 struct drm_i915_private *dev_priv = bus->dev_priv; 185 u32 reserved = get_reserved(bus); 186 u32 data_bits; 187 188 if (state_high) 189 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 190 else 191 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 192 GPIO_DATA_VAL_MASK; 193 194 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); 195 POSTING_READ(bus->gpio_reg); 196} 197 198static int 199intel_gpio_pre_xfer(device_t adapter) 200{ 201 struct intel_iic_softc *sc = device_get_softc(adapter); 202 struct intel_gmbus *bus = sc->bus; 203 struct drm_i915_private *dev_priv = bus->dev_priv; 204 205 intel_i2c_reset(dev_priv->dev); 206 intel_i2c_quirk_set(dev_priv, true); 207 IICBB_SETSDA(adapter, 1); 208 IICBB_SETSCL(adapter, 1); 209 udelay(I2C_RISEFALL_TIME); 210 return 0; 211} 212 213static void 214intel_gpio_post_xfer(device_t adapter) 215{ 216 struct intel_iic_softc *sc = device_get_softc(adapter); 217 struct intel_gmbus *bus = sc->bus; 218 struct drm_i915_private *dev_priv = bus->dev_priv; 219 220 IICBB_SETSDA(adapter, 1); 221 IICBB_SETSCL(adapter, 1); 222 intel_i2c_quirk_set(dev_priv, false); 223} 224 225static void 226intel_gpio_setup(struct intel_gmbus *bus, u32 pin) 227{ 228 struct drm_i915_private *dev_priv = bus->dev_priv; 229 230 /* -1 to map pin pair to gmbus index */ 231 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; 232} 233 234static int 235gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg, 236 u32 gmbus1_index) 237{ 238 int reg_offset = dev_priv->gpio_mmio_base; 239 u16 len = msg->len; 240 u8 *buf = msg->buf; 241 242 I915_WRITE(GMBUS1 + reg_offset, 243 gmbus1_index | 244 GMBUS_CYCLE_WAIT | 245 (len << GMBUS_BYTE_COUNT_SHIFT) | 246 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 247 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 248 while (len) { 249 int ret; 250 u32 val, loop = 0; 251 u32 gmbus2; 252 253 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & 254 (GMBUS_SATOER | GMBUS_HW_RDY), 255 50); 256 if (ret) 257 return -ETIMEDOUT; 258 if (gmbus2 & GMBUS_SATOER) 259 return -ENXIO; 260 261 val = I915_READ(GMBUS3 + reg_offset); 262 do { 263 *buf++ = val & 0xff; 264 val >>= 8; 265 } while (--len && ++loop < 4); 266 } 267 268 return 0; 269} 270 271static int 272gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg) 273{ 274 int reg_offset = dev_priv->gpio_mmio_base; 275 u16 len = msg->len; 276 u8 *buf = msg->buf; 277 u32 val, loop; 278 279 val = loop = 0; 280 while (len && loop < 4) { 281 val |= *buf++ << (8 * loop++); 282 len -= 1; 283 } 284 285 I915_WRITE(GMBUS3 + reg_offset, val); 286 I915_WRITE(GMBUS1 + reg_offset, 287 GMBUS_CYCLE_WAIT | 288 (msg->len << GMBUS_BYTE_COUNT_SHIFT) | 289 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 290 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 291 while (len) { 292 int ret; 293 u32 gmbus2; 294 295 val = loop = 0; 296 do { 297 val |= *buf++ << (8 * loop); 298 } while (--len && ++loop < 4); 299 300 I915_WRITE(GMBUS3 + reg_offset, val); 301 302 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & 303 (GMBUS_SATOER | GMBUS_HW_RDY), 304 50); 305 if (ret) 306 return -ETIMEDOUT; 307 if (gmbus2 & GMBUS_SATOER) 308 return -ENXIO; 309 } 310 return 0; 311} 312 313/* 314 * The gmbus controller can combine a 1 or 2 byte write with a read that 315 * immediately follows it by using an "INDEX" cycle. 316 */ 317static bool 318gmbus_is_index_read(struct iic_msg *msgs, int i, int num) 319{ 320 return (i + 1 < num && 321 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 322 (msgs[i + 1].flags & I2C_M_RD)); 323} 324 325static int 326gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs) 327{ 328 int reg_offset = dev_priv->gpio_mmio_base; 329 u32 gmbus1_index = 0; 330 u32 gmbus5 = 0; 331 int ret; 332 333 if (msgs[0].len == 2) 334 gmbus5 = GMBUS_2BYTE_INDEX_EN | 335 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 336 if (msgs[0].len == 1) 337 gmbus1_index = GMBUS_CYCLE_INDEX | 338 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 339 340 /* GMBUS5 holds 16-bit index */ 341 if (gmbus5) 342 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 343 344 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 345 346 /* Clear GMBUS5 after each index transfer */ 347 if (gmbus5) 348 I915_WRITE(GMBUS5 + reg_offset, 0); 349 350 return ret; 351} 352 353static int 354gmbus_xfer(device_t adapter, 355 struct iic_msg *msgs, 356 uint32_t num) 357{ 358 struct intel_iic_softc *sc = device_get_softc(adapter); 359 struct intel_gmbus *bus = sc->bus; 360 struct drm_i915_private *dev_priv = bus->dev_priv; 361 int i, reg_offset; 362 int ret = 0; 363 364 sx_xlock(&dev_priv->gmbus_mutex); 365 366 if (bus->force_bit) { 367 ret = -IICBUS_TRANSFER(bus->bbbus, msgs, num); 368 goto out; 369 } 370 371 reg_offset = dev_priv->gpio_mmio_base; 372 373 I915_WRITE(GMBUS0 + reg_offset, bus->reg0); 374 375 for (i = 0; i < num; i++) { 376 u32 gmbus2; 377 378 if (gmbus_is_index_read(msgs, i, num)) { 379 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 380 i += 1; /* set i to the index of the read xfer */ 381 } else if (msgs[i].flags & I2C_M_RD) { 382 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 383 } else { 384 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 385 } 386 387 if (ret == -ETIMEDOUT) 388 goto timeout; 389 if (ret == -ENXIO) 390 goto clear_err; 391 392 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & 393 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 394 50); 395 if (ret) 396 goto timeout; 397 if (gmbus2 & GMBUS_SATOER) 398 goto clear_err; 399 } 400 401 /* Generate a STOP condition on the bus. Note that gmbus can't generata 402 * a STOP on the very first cycle. To simplify the code we 403 * unconditionally generate the STOP condition with an additional gmbus 404 * cycle. */ 405 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 406 407 /* Mark the GMBUS interface as disabled after waiting for idle. 408 * We will re-enable it at the start of the next xfer, 409 * till then let it sleep. 410 */ 411 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 412 10)) { 413 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 414 device_get_desc(adapter)); 415 ret = -ETIMEDOUT; 416 } 417 I915_WRITE(GMBUS0 + reg_offset, 0); 418 goto out; 419 420clear_err: 421 /* 422 * Wait for bus to IDLE before clearing NAK. 423 * If we clear the NAK while bus is still active, then it will stay 424 * active and the next transaction may fail. 425 * 426 * If no ACK is received during the address phase of a transaction, the 427 * adapter must report -ENXIO. It is not clear what to return if no ACK 428 * is received at other times. But we have to be careful to not return 429 * spurious -ENXIO because that will prevent i2c and drm edid functions 430 * from retrying. So return -ENXIO only when gmbus properly quiescents - 431 * timing out seems to happen when there _is_ a ddc chip present, but 432 * it's slow responding and only answers on the 2nd retry. 433 */ 434 ret = -ENXIO; 435 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 436 10)) { 437 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 438 device_get_desc(adapter)); 439 ret = -ETIMEDOUT; 440 } 441 442 /* Toggle the Software Clear Interrupt bit. This has the effect 443 * of resetting the GMBUS controller and so clearing the 444 * BUS_ERROR raised by the slave's NAK. 445 */ 446 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 447 I915_WRITE(GMBUS1 + reg_offset, 0); 448 I915_WRITE(GMBUS0 + reg_offset, 0); 449 450 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 451 device_get_desc(adapter), msgs[i].slave >> 1, 452 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 453 454 goto out; 455 456timeout: 457 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 458 device_get_desc(adapter), bus->reg0 & 0xff); 459 I915_WRITE(GMBUS0 + reg_offset, 0); 460 461 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 462 bus->force_bit = 1; 463 ret = -IICBUS_TRANSFER(bus->bbbus, msgs, num); 464 465out: 466 sx_xunlock(&dev_priv->gmbus_mutex); 467 return -ret; 468} 469 470static int 471intel_gmbus_probe(device_t dev) 472{ 473 474 return (BUS_PROBE_SPECIFIC); 475} 476 477static int 478intel_gmbus_attach(device_t idev) 479{ 480 struct intel_iic_softc *sc; 481 struct drm_device *dev; 482 struct drm_i915_private *dev_priv; 483 int pin, port; 484 485 sc = device_get_softc(idev); 486 pin = device_get_unit(idev); 487 port = pin + 1; /* +1 to map gmbus index to pin pair */ 488 489 snprintf(sc->name, sizeof(sc->name), "i915 gmbus %s", 490 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name : 491 "reserved"); 492 device_set_desc(idev, sc->name); 493 494 dev = device_get_softc(device_get_parent(idev)); 495 dev_priv = dev->dev_private; 496 sc->bus = &dev_priv->gmbus[pin]; 497 498 /* add bus interface device */ 499 sc->iic_dev = device_add_child(idev, "iicbus", -1); 500 if (sc->iic_dev == NULL) 501 return (ENXIO); 502 device_quiet(sc->iic_dev); 503 bus_generic_attach(idev); 504 505 return (0); 506} 507 508static int 509intel_gmbus_detach(device_t idev) 510{ 511 512 bus_generic_detach(idev); 513 device_delete_children(idev); 514 515 return (0); 516} 517 518static device_method_t intel_gmbus_methods[] = { 519 DEVMETHOD(device_probe, intel_gmbus_probe), 520 DEVMETHOD(device_attach, intel_gmbus_attach), 521 DEVMETHOD(device_detach, intel_gmbus_detach), 522 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 523 DEVMETHOD(iicbus_transfer, gmbus_xfer), 524 DEVMETHOD_END 525}; 526static driver_t intel_gmbus_driver = { 527 "intel_gmbus", 528 intel_gmbus_methods, 529 sizeof(struct intel_iic_softc) 530}; 531static devclass_t intel_gmbus_devclass; 532DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver, 533 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 534DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0); 535 536static int 537intel_iicbb_probe(device_t dev) 538{ 539 540 return (BUS_PROBE_DEFAULT); 541} 542 543static int 544intel_iicbb_attach(device_t idev) 545{ 546 struct intel_iic_softc *sc; 547 struct drm_device *dev; 548 struct drm_i915_private *dev_priv; 549 int pin, port; 550 551 sc = device_get_softc(idev); 552 pin = device_get_unit(idev); 553 port = pin + 1; 554 555 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", 556 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name : 557 "reserved"); 558 device_set_desc(idev, sc->name); 559 560 dev = device_get_softc(device_get_parent(idev)); 561 dev_priv = dev->dev_private; 562 sc->bus = &dev_priv->gmbus[pin]; 563 564 /* add generic bit-banging code */ 565 sc->iic_dev = device_add_child(idev, "iicbb_nostop", -1); 566 if (sc->iic_dev == NULL) 567 return (ENXIO); 568 device_quiet(sc->iic_dev); 569 bus_generic_attach(idev); 570 571 return (0); 572} 573 574static int 575intel_iicbb_detach(device_t idev) 576{ 577 578 bus_generic_detach(idev); 579 device_delete_children(idev); 580 581 return (0); 582} 583 584static device_method_t intel_iicbb_methods[] = { 585 DEVMETHOD(device_probe, intel_iicbb_probe), 586 DEVMETHOD(device_attach, intel_iicbb_attach), 587 DEVMETHOD(device_detach, intel_iicbb_detach), 588 589 DEVMETHOD(bus_add_child, bus_generic_add_child), 590 DEVMETHOD(bus_print_child, bus_generic_print_child), 591 592 DEVMETHOD(iicbb_callback, iicbus_null_callback), 593 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 594 DEVMETHOD(iicbb_setsda, set_data), 595 DEVMETHOD(iicbb_setscl, set_clock), 596 DEVMETHOD(iicbb_getsda, get_data), 597 DEVMETHOD(iicbb_getscl, get_clock), 598 DEVMETHOD(iicbb_pre_xfer, intel_gpio_pre_xfer), 599 DEVMETHOD(iicbb_post_xfer, intel_gpio_post_xfer), 600 DEVMETHOD_END 601}; 602static driver_t intel_iicbb_driver = { 603 "intel_iicbb", 604 intel_iicbb_methods, 605 sizeof(struct intel_iic_softc) 606}; 607static devclass_t intel_iicbb_devclass; 608DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver, 609 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 610 611/* 612 * XXX This is a copy of struct iicbb_softc in sys/dev/iicbus/iicbb.c. 613 * There should really be a shared definition. 614 */ 615struct iicbb_softc { 616 device_t iicbus; 617 int udelay; /* signal toggle delay in usec */ 618}; 619 620static int 621iicbb_nostop_transfer_impl(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 622{ 623 int i, error, lenread, lenwrote, addr; 624 struct iicbb_softc *sc; 625 device_t bus; 626 bool started; 627 628 sc = device_get_softc(dev); 629 bus = sc->iicbus; 630 started = false; 631 for (i = 0, error = 0; i < nmsgs && error == 0; i++) { 632 addr = msgs[i].slave; 633 if (msgs[i].flags & IIC_M_RD) 634 addr |= LSB; 635 else 636 addr &= ~LSB; 637 638 if ((msgs[i].flags & IIC_M_NOSTART) == 0) { 639 if (i == 0) 640 error = iicbus_start(bus, addr, 0); 641 else 642 error = iicbus_repeated_start(bus, addr, 0); 643 if (error != 0) 644 break; 645 started = true; 646 } 647 648 if ((msgs[i].flags & IIC_M_RD) != 0) 649 error = iicbus_read(bus, msgs[i].buf, msgs[i].len, 650 &lenread, IIC_LAST_READ, 0); 651 else 652 error = iicbus_write(bus, msgs[i].buf, msgs[i].len, 653 &lenwrote, 0); 654 } 655 if (started) 656 iicbus_stop(bus); 657 return (error); 658} 659 660static int 661iicbb_nostop_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 662{ 663 int error; 664 665 error = IICBB_PRE_XFER(device_get_parent(dev)); 666 if (error) 667 return (error); 668 669 error = iicbb_nostop_transfer_impl(dev, msgs, nmsgs); 670 671 IICBB_POST_XFER(device_get_parent(dev)); 672 return (error); 673} 674 675static device_method_t iicbb_nostop_methods[] = { 676 DEVMETHOD(iicbus_transfer, iicbb_nostop_transfer), 677 678 DEVMETHOD_END 679}; 680 681static devclass_t iicbb_nostop_devclass; 682 683DEFINE_CLASS_1(iicbb_nostop, iicbb_nostop_driver, iicbb_nostop_methods, 684 sizeof(struct iicbb_softc), iicbb_driver); 685DRIVER_MODULE(iicbb_nostop, intel_iicbb, iicbb_nostop_driver, 686 iicbb_nostop_devclass, NULL, NULL); 687 688/** 689 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 690 * @dev: DRM device 691 */ 692int intel_setup_gmbus(struct drm_device *dev) 693{ 694 struct drm_i915_private *dev_priv = dev->dev_private; 695 device_t iic_dev; 696 int ret, i; 697 698 if (HAS_PCH_SPLIT(dev)) 699 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 700 else 701 dev_priv->gpio_mmio_base = 0; 702 703 sx_init(&dev_priv->gmbus_mutex, "gmbus"); 704 705 /* 706 * The Giant there is recursed, most likely. Normally, the 707 * intel_setup_gmbus() is called from the attach method of the 708 * driver. 709 */ 710 mtx_lock(&Giant); 711 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 712 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 713 u32 port = i + 1; /* +1 to map gmbus index to pin pair */ 714 715 bus->dev_priv = dev_priv; 716 717 /* By default use a conservative clock rate */ 718 bus->reg0 = port | GMBUS_RATE_100KHZ; 719 720 /* gmbus seems to be broken on i830 */ 721 if (IS_I830(dev)) 722 bus->force_bit = 1; 723 724 intel_gpio_setup(bus, port); 725 726 /* 727 * bbbus_bridge 728 * 729 * Initialized bbbus_bridge before gmbus_bridge, since 730 * gmbus may decide to force quirk transfer in the 731 * attachment code. 732 */ 733 bus->bbbus_bridge = device_add_child(dev->dev, 734 "intel_iicbb", i); 735 if (bus->bbbus_bridge == NULL) { 736 DRM_ERROR("bbbus bridge %d creation failed\n", i); 737 ret = -ENXIO; 738 goto err; 739 } 740 device_quiet(bus->bbbus_bridge); 741 ret = -device_probe_and_attach(bus->bbbus_bridge); 742 if (ret != 0) { 743 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 744 ret); 745 goto err; 746 } 747 748 /* bbbus */ 749 iic_dev = device_find_child(bus->bbbus_bridge, 750 "iicbb_nostop", -1); 751 if (iic_dev == NULL) { 752 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 753 goto err; 754 } 755 iic_dev = device_find_child(iic_dev, "iicbus", -1); 756 if (iic_dev == NULL) { 757 DRM_ERROR( 758 "bbbus bridge doesn't have iicbus grandchild\n"); 759 goto err; 760 } 761 762 bus->bbbus = iic_dev; 763 764 /* gmbus_bridge */ 765 bus->gmbus_bridge = device_add_child(dev->dev, 766 "intel_gmbus", i); 767 if (bus->gmbus_bridge == NULL) { 768 DRM_ERROR("gmbus bridge %d creation failed\n", i); 769 ret = -ENXIO; 770 goto err; 771 } 772 device_quiet(bus->gmbus_bridge); 773 ret = -device_probe_and_attach(bus->gmbus_bridge); 774 if (ret != 0) { 775 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 776 ret); 777 ret = -ENXIO; 778 goto err; 779 } 780 781 /* gmbus */ 782 iic_dev = device_find_child(bus->gmbus_bridge, 783 "iicbus", -1); 784 if (iic_dev == NULL) { 785 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 786 goto err; 787 } 788 789 bus->gmbus = iic_dev; 790 } 791 mtx_unlock(&Giant); 792 793 intel_i2c_reset(dev_priv->dev); 794 795 return 0; 796 797err: 798 while (--i) { 799 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 800 if (bus->gmbus_bridge != NULL) 801 device_delete_child(dev->dev, bus->gmbus_bridge); 802 if (bus->bbbus_bridge != NULL) 803 device_delete_child(dev->dev, bus->bbbus_bridge); 804 } 805 mtx_unlock(&Giant); 806 sx_destroy(&dev_priv->gmbus_mutex); 807 return ret; 808} 809 810device_t intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 811 unsigned port) 812{ 813 WARN_ON(!intel_gmbus_is_port_valid(port)); 814 /* -1 to map pin pair to gmbus index */ 815 return (intel_gmbus_is_port_valid(port)) ? 816 dev_priv->gmbus[port - 1].gmbus : NULL; 817} 818 819void intel_gmbus_set_speed(device_t adapter, int speed) 820{ 821 struct intel_gmbus *bus = to_intel_gmbus(adapter); 822 823 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 824} 825 826void intel_gmbus_force_bit(device_t adapter, bool force_bit) 827{ 828 struct intel_gmbus *bus = to_intel_gmbus(adapter); 829 830 bus->force_bit += force_bit ? 1 : -1; 831 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 832 force_bit ? "en" : "dis", device_get_desc(adapter), 833 bus->force_bit); 834} 835 836void intel_teardown_gmbus(struct drm_device *dev) 837{ 838 struct drm_i915_private *dev_priv = dev->dev_private; 839 int i; 840 int ret; 841 842 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 843 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 844 845 mtx_lock(&Giant); 846 ret = device_delete_child(dev->dev, bus->gmbus_bridge); 847 mtx_unlock(&Giant); 848 849 KASSERT(ret == 0, ("unable to detach iic gmbus %s: %d", 850 device_get_desc(bus->gmbus_bridge), ret)); 851 852 mtx_lock(&Giant); 853 ret = device_delete_child(dev->dev, bus->bbbus_bridge); 854 mtx_unlock(&Giant); 855 856 KASSERT(ret == 0, ("unable to detach iic bbbus %s: %d", 857 device_get_desc(bus->bbbus_bridge), ret)); 858 } 859 860 sx_destroy(&dev_priv->gmbus_mutex); 861} 862