/linux-master/drivers/phy/renesas/ |
H A D | phy-rcar-gen3-pcie.c | 16 #define PHY_CTRL 0x4000 /* R8A77980 only */ macro 18 /* PHY control register (PHY_CTRL) */ 48 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); 56 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN);
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/linux-master/drivers/phy/broadcom/ |
H A D | phy-bcm-sr-usb.c | 21 PHY_CTRL, enumerator in enum:bcm_usb_phy_reg 29 [PHY_CTRL] = 0x14, 34 [PHY_CTRL] = 0x10, 39 [PHY_CTRL] = 0xc, 134 rd_data = readl(regs + offset[PHY_CTRL]); 137 writel(rd_data, regs + offset[PHY_CTRL]); 183 bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL], 185 bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
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/linux-master/drivers/phy/freescale/ |
H A D | phy-fsl-imx8qm-lvds-phy.c | 21 #define PHY_CTRL 0x0 macro 72 PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL); 117 regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); 127 regmap_write(priv->regmap, PHY_CTRL + REG_SET, val); 154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, 157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, 287 regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL); 405 regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD); 417 regmap_update_bits(priv->regmap, PHY_CTRL,
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H A D | phy-fsl-imx8-mipi-dphy.c | 25 #define PHY_CTRL 0x00 macro 395 regmap_write(priv->lvds_regmap, PHY_CTRL, 545 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN); 602 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0);
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/linux-master/drivers/net/ethernet/intel/e1000/ |
H A D | e1000_ethtool.c | 1169 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); 1181 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1183 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); 1189 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1217 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); 1219 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); 1225 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); 1295 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1297 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); 1347 e1000_read_phy_reg(hw, PHY_CTRL, [all...] |
H A D | e1000_main.c | 423 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); 425 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); 460 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); 462 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); 4702 !e1000_read_phy_reg(hw, PHY_CTRL, 4706 e1000_write_phy_reg(hw, PHY_CTRL, 4717 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { 4720 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); 4791 case PHY_CTRL: 4826 case PHY_CTRL [all...] |
H A D | e1000_hw.c | 1340 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1345 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1668 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1755 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1926 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3109 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3114 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
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H A D | e1000_hw.h | 2478 #define PHY_CTRL 0x00 /* Control Register */ macro
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/linux-master/drivers/gpu/drm/loongson/ |
H A D | lsdc_output_7a2000.c | 92 LSDC_HDMI_REG(0, PHY_CTRL), 104 LSDC_HDMI_REG(1, PHY_CTRL),
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/linux-master/drivers/net/ethernet/intel/e1000e/ |
H A D | ich8lan.c | 2406 mac_reg = er32(PHY_CTRL); 3033 phy_ctrl = er32(PHY_CTRL); 3037 ew32(PHY_CTRL, phy_ctrl); 3058 ew32(PHY_CTRL, phy_ctrl); 3116 phy_ctrl = er32(PHY_CTRL); 3120 ew32(PHY_CTRL, phy_ctrl); 3157 ew32(PHY_CTRL, phy_ctrl); 5245 phy_ctrl = er32(PHY_CTRL); 5248 ew32(PHY_CTRL, phy_ctrl); 5302 reg = er32(PHY_CTRL); [all...] |
H A D | phy.c | 2694 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
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/linux-master/drivers/mmc/host/ |
H A D | sdhci-pci-arasan.c | 44 #define PHY_CTRL 0x24 macro
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/linux-master/drivers/scsi/hisi_sas/ |
H A D | hisi_sas_v1_hw.c | 126 #define PHY_CTRL (PORT_BASE + 0x14) macro 566 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); 569 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
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H A D | hisi_sas_v2_hw.c | 181 #define PHY_CTRL (PORT_BASE + 0x14) macro 1266 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
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H A D | hisi_sas_v3_hw.c | 200 #define PHY_CTRL (PORT_BASE + 0x14) macro 2957 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
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/linux-master/drivers/mtd/nand/raw/ |
H A D | cadence-nand-controller.c | 264 #define PHY_CTRL 0x2080 macro 1333 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
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/linux-master/drivers/media/i2c/ccs/ |
H A D | ccs-core.c | 1540 return ccs_write(sensor, PHY_CTRL, val);
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