Searched refs:PHYDSYMCLK_CLOCK_CNTL (Results 1 - 8 of 8) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.h | 40 SR(PHYDSYMCLK_CLOCK_CNTL),\
87 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
88 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
|
| H A D | dcn31_dccg.c | 505 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
512 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dccg.h | 46 SR(PHYDSYMCLK_CLOCK_CNTL),\
182 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
183 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dccg.h | 66 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
67 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
145 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
146 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
|
| H A D | dcn35_dccg.c | 440 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
444 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dccg.h | 53 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
54 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.h | 360 uint32_t PHYDSYMCLK_CLOCK_CNTL; member in struct:dccg_registers
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 1226 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \
|
Completed in 126 milliseconds