Searched refs:PHYCSYMCLK_CLOCK_CNTL (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.h36 SR(PHYCSYMCLK_CLOCK_CNTL)
47 SR(PHYCSYMCLK_CLOCK_CNTL)
57 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
58 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
66 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
67 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.h39 SR(PHYCSYMCLK_CLOCK_CNTL),\
85 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
86 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
H A Ddcn31_dccg.c488 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
495 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.h45 SR(PHYCSYMCLK_CLOCK_CNTL),\
180 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
181 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.h64 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
65 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
143 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
144 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
H A Ddcn35_dccg.c429 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
433 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.h51 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
52 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h359 uint32_t PHYCSYMCLK_CLOCK_CNTL; member in struct:dccg_registers
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h1226 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \

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