Searched refs:OS_REG_SET_BIT (Results 1 - 25 of 48) sorted by relevance

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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar9002/
H A Dar9287_cal.c56 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
H A Dar9285_cal.c169 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
171 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
172 OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
176 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
188 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
189 OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
190 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
198 OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
H A Dar9287_olc.c49 OS_REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/
H A Dar5416_power.c59 OS_REG_SET_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
61 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
72 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
96 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
116 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
H A Dar5416_radar.c158 OS_REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
163 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128);
168 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI);
173 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK);
191 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1,
198 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1,
217 OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
H A Dar5416_cal.c130 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);
212 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
217 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
229 OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL,
271 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
583 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
584 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
585 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
650 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
H A Dar5416_beacon.c73 OS_REG_SET_BIT(ah, AR_TIMER_MODE,
105 OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);
270 OS_REG_SET_BIT(ah, AR_TIMER_MODE,
H A Dar5416_cal_iq.c132 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
H A Dar5416_cal_adcdc.c111 OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
H A Dar5416_cal_adcgain.c116 OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
H A Dar5416_misc.c407 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
413 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
440 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
513 OS_REG_SET_BIT(ah, AR_MISC_MODE,
H A Dar5416_btcoex.c343 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
382 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
H A Dar5416_reset.c192 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
198 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
200 OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
203 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
377 OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
385 OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
581 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1468 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
1484 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2629 OS_REG_SET_BIT(a
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_timer.c98 OS_REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
99 OS_REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
128 OS_REG_SET_BIT(ah,
142 OS_REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, (1 << index));
147 OS_REG_SET_BIT(ah, AR_IMR_S5,
H A Dar9300_beacon.c44 OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
74 OS_REG_SET_BIT(ah, AR_TIMER_MODE,
195 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN
H A Dar9300_recv.c72 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
188 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
271 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
H A Dar9300_xmit.c681 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
695 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
786 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
800 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
877 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
879 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
890 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
H A Dar9300_power.c469 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_REQ);
470 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_INT_EMB_CPU);
514 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
524 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
548 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
600 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
988 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1379 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1402 //OS_REG_SET_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE);
H A Dar9300_reset.c1377 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
2140 OS_REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
2294 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2401 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2402 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2403 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2676 OS_REG_SET_BIT(ah,
2723 OS_REG_SET_BIT(ah,
2789 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2811 OS_REG_SET_BIT(a
[all...]
H A Dar9300_gpio.c179 OS_REG_SET_BIT(ah,
356 OS_REG_SET_BIT(ah,
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/
H A Dar5210_power.c36 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);
90 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/
H A Dar5211_power.c79 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
92 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/
H A Dar5212_power.c99 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
112 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
H A Dar5212_reset.c548 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
799 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
819 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1020 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
1063 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
1081 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
1144 OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD);
1150 OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M);
1455 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1471 OS_REG_SET_BIT(a
[all...]
H A Dar5212_misc.c160 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
540 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
1198 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1205 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1212 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1219 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1226 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,

Completed in 157 milliseconds

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