Searched refs:LinkLevel (Results 1 - 14 of 14) sorted by last modified time

/linux-master/drivers/gpu/drm/radeon/
H A Dsmu7_discrete.h312 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member in struct:SMU7_Discrete_DpmTable
H A Dci_dpm.c2590 table->LinkLevel[i].PcieGenSpeed =
2592 table->LinkLevel[i].PcieLaneCount =
2594 table->LinkLevel[i].EnabledForActivity = 1;
2595 table->LinkLevel[i].DownT = cpu_to_be32(5);
2596 table->LinkLevel[i].UpT = cpu_to_be32(30);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c773 table->LinkLevel[i].PcieGenSpeed =
775 table->LinkLevel[i].PcieLaneCount =
777 table->LinkLevel[i].EnabledForActivity =
779 table->LinkLevel[i].SPC =
781 table->LinkLevel[i].DownThreshold =
783 table->LinkLevel[i].UpThreshold =
H A Dci_smumgr.c1006 table->LinkLevel[i].PcieGenSpeed =
1008 table->LinkLevel[i].PcieLaneCount =
1010 table->LinkLevel[i].EnabledForActivity = 1;
1011 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
1012 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
H A Dvegam_smumgr.c580 table->LinkLevel[i].PcieGenSpeed =
582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
584 table->LinkLevel[i].EnabledForActivity = 1;
585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
586 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
587 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
2114 table->LinkLevel[i - 1].BifSclkDfs =
H A Dtonga_smumgr.c516 table->LinkLevel[i].PcieGenSpeed =
518 table->LinkLevel[i].PcieLaneCount =
520 table->LinkLevel[i].EnabledForActivity =
522 table->LinkLevel[i].SPC =
524 table->LinkLevel[i].DownThreshold =
526 table->LinkLevel[i].UpThreshold =
H A Dpolaris10_smumgr.c826 table->LinkLevel[i].PcieGenSpeed =
828 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
830 table->LinkLevel[i].EnabledForActivity = 1;
831 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
832 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
833 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
2100 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
H A Dfiji_smumgr.c837 table->LinkLevel[i].PcieGenSpeed =
839 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
841 table->LinkLevel[i].EnabledForActivity = 1;
842 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
843 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
844 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu73_discrete.h242 SMU73_Discrete_LinkLevel LinkLevel[SMU73_MAX_LEVELS_LINK]; member in struct:SMU73_Discrete_DpmTable
H A Dsmu7_discrete.h326 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member in struct:SMU7_Discrete_DpmTable
H A Dsmu75_discrete.h290 SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK]; member in struct:SMU75_Discrete_DpmTable
H A Dsmu74_discrete.h285 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK]; member in struct:SMU74_Discrete_DpmTable
H A Dsmu72_discrete.h268 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; member in struct:SMU72_Discrete_DpmTable
H A Dsmu71_discrete.h273 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK]; member in struct:SMU71_Discrete_DpmTable

Completed in 333 milliseconds