Searched refs:L3BANK (Results 1 - 5 of 5) sorted by relevance
| /linux-master/drivers/gpu/drm/xe/ |
| H A D | xe_gt_mcr.c | 96 { 0x00B100, 0x00B3FF }, /* L3BANK */
210 { 0x00B000, 0x00B3FF }, /* NODE, L3BANK */
230 { 0x38B600, 0x38B8FF }, /* L3BANK */
249 gt->steering[L3BANK].group_target = __ffs(mslice_mask);
250 gt->steering[L3BANK].instance_target =
259 * the first L3BANK of that quad. Access to the Nth L3 bank is
262 gt->steering[L3BANK].group_target = (bank >> 2) & 0x7;
263 gt->steering[L3BANK].instance_target = bank & 0x3;
268 gt->steering[L3BANK].group_target = 0; /* unused */
269 gt->steering[L3BANK]
[all...] |
| H A D | xe_gt_types.h | 53 L3BANK, enumerator in enum:xe_steering_type
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| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_types.h | 60 L3BANK, enumerator in enum:intel_steering_type
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| H A D | intel_gt_mcr.c | 41 "L3BANK",
94 { 0x00B100, 0x00B3FF }, /* L3BANK */
186 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
204 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
639 case L3BANK:
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| H A D | intel_workarounds.c | 1287 * worry about explicitly re-steering L3BANK reads later.
1290 gt->steering_table[L3BANK] = NULL;
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