Searched refs:I915_MAX_PIPES (Results 1 - 24 of 24) sorted by relevance
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_bw.h | 26 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; 56 int min_cdclk[I915_MAX_PIPES]; 57 unsigned int data_rate[I915_MAX_PIPES]; 58 u8 num_active_planes[I915_MAX_PIPES];
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H A D | skl_watermark.h | 57 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 58 unsigned int weight[I915_MAX_PIPES]; 59 u8 slices[I915_MAX_PIPES];
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H A D | intel_link_bw.h | 22 int max_bpp_x16[I915_MAX_PIPES];
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H A D | intel_display_irq.h | 73 void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 75 void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 76 void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 77 void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]); 78 void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]);
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H A D | intel_display_limits.h | 23 I915_MAX_PIPES = _PIPE_EDP enumerator in enum:pipe
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H A D | intel_cdclk.h | 44 int min_cdclk[I915_MAX_PIPES]; 46 u8 min_voltage_level[I915_MAX_PIPES];
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H A D | intel_pmdemand.h | 37 int ddi_clocks[I915_MAX_PIPES];
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H A D | intel_display_core.h | 460 u32 de_irq_mask[I915_MAX_PIPES]; 461 u32 pipestat_irq_mask[I915_MAX_PIPES]; 530 u32 chv_dpll_md[I915_MAX_PIPES];
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H A D | intel_display_device.h | 124 u8 num_sprites[I915_MAX_PIPES]; 125 u8 num_scalers[I915_MAX_PIPES]; 155 u32 cursor_offsets[I915_MAX_PIPES];
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H A D | intel_frontbuffer.c | 329 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 331 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32);
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H A D | intel_dp_tunnel.c | 20 struct drm_dp_tunnel_ref ref[I915_MAX_PIPES]; 469 drm_WARN_ON(&i915->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));
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H A D | intel_plane_initial.c | 415 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {};
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H A D | intel_display_irq.c | 410 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 476 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 493 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 517 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 544 u32 pipe_stats[I915_MAX_PIPES])
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H A D | intel_dvo.c | 420 u32 dpll[I915_MAX_PIPES];
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H A D | intel_display.h | 220 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
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H A D | intel_display_device.c | 963 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
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H A D | intel_display_types.h | 1782 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
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H A D | skl_watermark.c | 841 u8 dbuf_mask[I915_MAX_PIPES]; 3126 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3147 I915_MAX_PIPES, crtc->pipe))
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H A D | intel_display.c | 6986 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7038 entries, I915_MAX_PIPES, pipe)) 7126 entries, I915_MAX_PIPES, pipe)); 7224 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
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/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | fb_decoder.c | 190 for (i = 0; i < I915_MAX_PIPES; i++) 214 if (pipe >= I915_MAX_PIPES) 345 if (pipe >= I915_MAX_PIPES) 424 if (pipe >= I915_MAX_PIPES)
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H A D | gvt.h | 116 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
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H A D | display.c | 81 pipe < PIPE_A || pipe >= I915_MAX_PIPES))
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/linux-master/drivers/gpu/drm/xe/display/ |
H A D | xe_plane_initial.c | 275 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {};
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_irq.c | 264 u32 pipe_stats[I915_MAX_PIPES] = {}; 350 u32 pipe_stats[I915_MAX_PIPES] = {}; 1002 u32 pipe_stats[I915_MAX_PIPES] = {}; 1104 u32 pipe_stats[I915_MAX_PIPES] = {}; 1230 u32 pipe_stats[I915_MAX_PIPES] = {};
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