Searched refs:HIWORD_UPDATE (Results 1 - 25 of 36) sorted by relevance

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/linux-master/sound/soc/rockchip/
H A Drockchip_i2s_tdm.h288 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
291 #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
292 #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
293 #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
294 #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
303 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
304 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
305 #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
306 #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
315 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(
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/linux-master/drivers/soc/rockchip/
H A Dgrf.c14 #define HIWORD_UPDATE(val, mask, shift) \ macro
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
81 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
92 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
103 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
114 { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(
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/linux-master/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
H A Ddw-mipi-dsi-rockchip.c205 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1482 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1483 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1487 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1500 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1501 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1508 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1509 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1525 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1527 HIWORD_UPDATE(
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H A Ddw_hdmi-rockchip.c57 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
383 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
390 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
405 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
410 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
424 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
429 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
434 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
464 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
465 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SE
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H A Danalogix_dp-rockchip.c39 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
464 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
465 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
471 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
472 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
108 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
113 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
166 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
189 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
195 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
290 HIWORD_UPDATE(rk_phy->drive_impedance,
297 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
304 HIWORD_UPDATE(rk_phy->output_tapdelay_select,
311 HIWORD_UPDATE(rk_ph
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H A Dphy-rockchip-pcie.c25 #define HIWORD_UPDATE(val, mask, shift) \ macro
103 HIWORD_UPDATE(data,
106 HIWORD_UPDATE(addr,
111 HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
116 HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
131 HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
152 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
179 HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
185 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
236 HIWORD_UPDATE(PHY_CFG_PLL_LOC
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H A Dphy-rockchip-usb.c27 #define HIWORD_UPDATE(val, mask) \ macro
82 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
335 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
345 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
351 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
383 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
433 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
H A Dphy-rockchip-inno-csidphy.c74 #define HIWORD_UPDATE(val, mask, shift) \ macro
150 HIWORD_UPDATE(value, reg->mask, reg->shift));
/linux-master/drivers/clk/rockchip/
H A Dclk-pll.c214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
272 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
283 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
447 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
453 HIWORD_UPDATE(rat
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H A Dclk-cpu.c199 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
209 writel(HIWORD_UPDATE(reg_data->mux_core_alt,
214 writel(HIWORD_UPDATE(reg_data->mux_core_alt,
251 writel(HIWORD_UPDATE(reg_data->mux_core_main,
256 writel(HIWORD_UPDATE(reg_data->mux_core_main,
265 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
H A Dclk-inverter.c49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),
H A Dclk-mmc-phase.c138 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
H A Dclk-rk3588.c151 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
153 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
160 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
167 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
169 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
176 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
183 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
185 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
192 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
194 HIWORD_UPDATE(_divds
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H A Dclk-rk3188.c112 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
118 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
120 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
122 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
124 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
164 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
H A Dclk-rk3288.c138 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
140 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
146 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
148 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
150 HIWORD_UPDATE(_pclk_dbg_pre, \
H A Dclk-rk3036.c86 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
452 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
H A Dclk-rk3568.c119 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
121 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
123 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
130 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
137 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
139 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
146 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
148 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
H A Dclk-rk3228.c84 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
86 HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
H A Dclk-rk3128.c83 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
85 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
/linux-master/drivers/pci/controller/
H A Dpcie-rockchip.h22 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
23 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
33 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
39 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
43 #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
45 #define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c86 #define HIWORD_UPDATE(val, mask, shift) \ macro
163 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
164 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
272 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
273 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
418 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
419 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
558 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
559 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
710 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(va
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/linux-master/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c30 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
31 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
/linux-master/drivers/devfreq/event/
H A Drockchip-dfi.c33 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
145 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
163 writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
167 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
197 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),

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