#
a3561e77 |
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15-Mar-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: support more core div setting Use arrays to support more core independent div settings. A55 supports each core to work at different frequencies, and each core has an independent divider control. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210315085608.16010-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
0a7f99aa |
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03-Jul-2020 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
clk: rockchip: use separate compatibles for rk3288w-cru Commit 1627f683636d ("clk: rockchip: Handle clock tree for rk3288w variant") added the check for rk3288w-specific clock-tree changes but in turn would require a double-compatible due to re-using the main rockchip,rk3288-cru compatible as entry point. The binding change actually describes the compatibles as one or the other so adapt the code accordingly and add a real second entry-point for the clock controller. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rock-pi-n8 Link: https://lore.kernel.org/r/20200703154948.260369-1-heiko@sntech.de
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#
1627f683 |
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02-Jun-2020 |
Mylène Josserand <mylene.josserand@collabora.com> |
clk: rockchip: Handle clock tree for rk3288w variant The revision rk3288w has a different clock tree about "hclk_vio" clock, according to the BSP kernel code. This patch handles this difference by detecting which device-tree we are using. If it is a "rockchip,rk3288-cru", let's register the clock tree as it was before. If the device-tree node is "rockchip,rk3288w-cru", we will apply the difference with this version of this SoC. Noticed that this new device-tree compatible must be handled in bootloader such as u-boot. Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com> Link: https://lore.kernel.org/r/20200602080644.11333-2-mylene.josserand@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
e4488e45 |
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06-Jun-2019 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro Convert the boilerplate code for manual addition of the watchdog clock to the new SGRF_GATE macro for all affected socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
7d212931 |
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04-Jun-2019 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: Remove 48 MHz PLL rate from rk3288 The 48 MHz PLL rate is not present in the downstream chromeos-3.14 tree. Looking at history, it was originally removed in <https://crrev.com/c/265810> ("CHROMIUM: clk: rockchip: expand more clocks support") with no explanation. Much of that patch was later reverted in <https://crrev.com/c/284595> ("CHROMIUM: clk: rockchip: Revert more questionable PLL rates"), but that patch left in the removal of 48 MHz. What I wrote in that patch: > Note that the original change also removed the rate (48000000, 1, > 64, 32) from the table. I have no idea why that was squashed in > there, but that rate was invalid anyway (it appears to have an out > of bounds NO). I'm not putting that rate in. Reading the TRM I see that NO is defined as - NO: 1, 2-16 (even only) ...and furthermore only 4 bits are assigned for NO-1, which means that the highest NO we could even represent is 16. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
c942fddf |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
62e59c4e |
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18-Apr-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
f4033db5 |
|
12-Apr-2019 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: undo several noc and special clocks as critical on rk3288 This is mostly a revert of commit 55bb6a633c33 ("clk: rockchip: mark noc and some special clk as critical on rk3288") except that we're keeping "pmu_hclk_otg0" as critical still. NOTE: turning these clocks off doesn't seem to do a whole lot in terms of power savings (checking the power on the logic rail). It appears to save maybe 1-2mW. ...but still it seems like we should turn the clocks off if they aren't needed. About "pmu_hclk_otg0" (the one clock from the original commit we're still keeping critical) from an email thread: > pmu ahb clock > > Function: Clock to pmu module when hibernation and/or ADP is > enabled. Must be greater than or equal to 30 MHz. > > If the SOC design does not support hibernation/ADP function, only have > hclk_otg, this clk can be switched according to the usage of otg. > If the SOC design support hibernation/ADP, has two clocks, hclk_otg and > pmu_hclk_otg0. > Hclk_otg belongs to the closed part of otg logic, which can be switched > according to the use of otg. > > pmu_hclk_otg0 belongs to the always on part. > > As for whether pmu_hclk_otg0 can be turned off when otg is not in use, > we have not tested. IC suggest make pmu_hclk_otg0 always on. For the rest of the clocks: atclk: No documentation about this clock other than that it goes to the CPU. CPU functions fine without it on. Maybe needed for JTAG? jtag: Presumably this clock is only needed if you're debugging with JTAG. It doesn't seem like it makes sense to waste power for every rk3288 user. In any case to do JTAG you'd need private patches to adjust the pinctrl the mux the JTAG out anyway. pclk_dbg, pclk_core_niu: On veyron Chromebooks we turn these two clocks on only during kernel panics in order to access some coresight registers. Since nothing in the upstream kernel does this we should be able to leave them off safely. Maybe also needed for JTAG? hsicphy12m_xin12m: There is no indication of why this clock would need to be turned on for boards that don't use HSIC. pclk_ddrupctl[0-1], pclk_publ0[0-1]: On veyron Chromebooks we turn these 4 clocks on only when doing DDR transitions and they are off otherwise. I see no reason why they'd need to be on in the upstream kernel which doesn't support DDRFreq. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
57a20248 |
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11-Apr-2019 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 Experimentally it can be seen that going into deep sleep (specifically setting PMU_CLR_DMA and PMU_CLR_BUS in RK3288_PMU_PWRMODE_CON1) appears to fail unless "aclk_dmac1" is on. The failure is that the system never signals that it made it into suspend on the GLOBAL_PWROFF pin and it just hangs. NOTE that it's confirmed that it's the actual suspend that fails, not one of the earlier calls to read/write registers. Specifically if you comment out the "PMU_GLOBAL_INT_DISABLE" setting in rk3288_slp_mode_set() and then comment out the "cpu_do_idle()" call in rockchip_lpmode_enter() then you can exercise the whole suspend path without any crashing. This is currently not a problem with suspend upstream because there is no current way to exercise the deep suspend code. However, anyone trying to make it work will run into this issue. This was not a problem on shipping rk3288-based Chromebooks because those devices all ran on an old kernel based on 3.14. On that kernel "aclk_dmac1" appears to be left on all the time. There are several ways to skin this problem. A) We could add "aclk_dmac1" to the list of critical clocks and that apperas to work, but presumably that wastes power. B) We could keep a list of "struct clk" objects to enable at suspend time in clk-rk3288.c and use the standard clock APIs. C) We could make the rk3288-pmu driver keep a list of clocks to enable at suspend time. Presumably this would require a dts and bindings change. D) We could just whack the clock on in the existing syscore suspend function where we whack a bunch of other clocks. This is particularly easy because we know for sure that the clock's only parent ("aclk_cpu") is a critical clock so we don't need to do anything more than ungate it. In this case I have chosen D) because it seemed like the least work, but any of the other options would presumably also work fine. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
bf297420 |
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11-Apr-2019 |
Matthias Kaehlcke <mka@chromium.org> |
clk: rockchip: Limit use of USB PHY clock to USB on rk3288 The USB PHY clock can be configured as (grand) parent of uart0_sclk and sclk_gpu. It has been observed that UART0 doesn't work reliably in high speed mode with the PHY clock as input when certain USB devices are plugged to the USB HOST1 port (see https://crrev.com/c/320543). Prefix the name of the PHY clock with a '.' in the non-USB muxes to effectively remove the clock as input from these muxes. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
00c0cd9e |
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11-Apr-2019 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: Fix video codec clocks on rk3288 It appears that there is a typo in the rk3288 TRM. For GRF_SOC_CON0[7] it says that 0 means "vepu" and 1 means "vdpu". It's the other way around. How do I know? Here's my evidence: 1. Prior to commit 4d3e84f99628 ("clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288") we always pretended that we were using "aclk_vdpu" and the comment in the code said that this matched the default setting in the system. In fact the default setting is 0 according to the TRM and according to reading memory at bootup. In addition rk3288-based Chromebooks ran like this and the video codecs worked. 2. With the existing clock code if you boot up and try to enable the new VIDEO_ROCKCHIP_VPU as a module (and without "clk_ignore_unused" on the command line), you get errors like "failed to get ack on domain 'pd_video', val=0x80208". After flipping vepu/vdpu things init OK. 3. If I export and add both the vepu and vdpu to the list of clocks for RK3288_PD_VIDEO I can get past the power domain errors, but now I freeze when the vpu_mmu gets initted. 4. If I just mark the "vdpu" as IGNORE_UNUSED then everything boots up and probes OK showing that somehow the "vdpu" was important to keep enabled. This is because we were actually using it as a parent. 5. After this change I can hack "aclk_vcodec_pre" to parent from "aclk_vepu" using assigned-clocks and the video codec still probes OK. 6. Rockchip has said so on the mailing list [1]. ...so let's fix it. Let's also add CLK_SET_RATE_PARENT to "aclk_vcodec_pre" as suggested by Jonas Karlman. Prior to the same commit you could do clk_set_rate() on "aclk_vcodec" and it would change "aclk_vdpu". That's because "aclk_vcodec" was a simple gate clock (always gets CLK_SET_RATE_PARENT) and its direct parent was "aclk_vdpu". After that commit "aclk_vcodec_pre" gets in the way so we need to add CLK_SET_RATE_PARENT to it too. [1] https://lkml.kernel.org/r/1d17b015-9e17-34b9-baf8-c285dc1957aa@rock-chips.com Fixes: 4d3e84f99628 ("clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288") Suggested-by: Jonas Karlman <jonas@kwiboo.se> Suggested-by: Randy Li <ayaka@soulik.info> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
dfe7fb21 |
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09-Apr-2019 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: Make rkpwm a critical clock on rk3288 Most rk3288-based boards are derived from the EVB and thus use a PWM regulator for the logic rail. However, most rk3288-based boards don't specify the PWM regulator in their device tree. We'll deal with that by making it critical. NOTE: it's important to make it critical and not just IGNORE_UNUSED because all PWMs in the system share the same clock. We don't want another PWM user to turn the clock on and off and kill the logic rail. This change is in preparation for actually having the PWMs in the rk3288 device tree actually point to the proper PWM clock. Up until now they've all pointed to the clock for the old IP block and they've all worked due to the fact that rkpwm was IGNORE_UNUSED and that the clock rates for both clocks were the same. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
c14d28e8 |
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28-Aug-2018 |
Urja Rannikko <urjaman@gmail.com> |
clk: rockchip: improve rk3288 pll rates for better hdmi output Add and correct PLL rates for better hdmi output. This includes minimizing jitter on 213 MHz for better 71 MHz, 250.5 MHz for better 83.5 MHz, 428 MHz for better 25.175 Mhz, low jitter 273 MHz for better 68.25 mhz, 356 MHz for better 118.68 Mhz and 300MHz. Increase the used Fvco for 308, 324 MHz, 292.5 MHz, 273.6 MHz, 238 MHz and 216 MHz. And add some additional rates allowing to reach better hdmi-related rates in general. These match the rates used by ChromeOS, so have been quite widely tested. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
55bb6a63 |
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02-May-2017 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: mark noc and some special clk as critical on rk3288 The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them. But this clks need enable,so make it as ignore_unused for now. The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
a8114989 |
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17-Jan-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
clk: rockchip: rk3288: make all niu clocks critical NIU clocks are related to the interconnect and it's important to other blocks. Since we don't have a driver to handle it, we should always enable it to avoid casually close. Make all of them critical,so that we don't have to each clock on its own once things break. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> [dropped the matching CLK_IGNORE_UNUSED flags] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
cf9790e0 |
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17-Jan-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
clk: rockchip: use rk3288 vip_out clock ids Reference the newly added vip clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
c5d032d3 |
|
10-Jan-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
clk: rockchip: use rk3288 isp_in clock ids Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
4d3e84f9 |
|
26-Dec-2016 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
1d003eb0 |
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12-Mar-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
clk: rockchip: release io resource when failing to init clk We should call iounmap to relase reg_base since it's not going to be used any more if failing to init clk. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
ef1d9fee |
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08-Mar-2016 |
Xing Zheng <zhengxing@rock-chips.com> |
clk: rockchip: Add support for multiple clock providers There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
268aebaa |
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08-Mar-2016 |
Xing Zheng <zhengxing@rock-chips.com> |
clk: rockchip: allow varying mux parameters for cpuclk pll-sources Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
36714529 |
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20-Jun-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: convert manually created factor clocks to the new type Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
219a5859 |
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19-Nov-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: fix usbphy-related clocks The otgphy clocks really only drive the phy blocks. These in turn contain plls that then generate the 480m clocks the clock controller uses to supply some other clocks like uart0, gpu or the video-codec. So fix this structure to actually respect that hirarchy and removed that usb480m fixed-rate clock working as a placeholder till now, as this wouldn't even work if the supplying phy gets turned off while its pll-output gets used elsewhere. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Michael Turquette <mturquette@baylibre.com>
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#
5b738403 |
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26-Dec-2015 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: fix section mismatches with new child-clocks To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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#
84a8c541 |
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22-Dec-2015 |
Sjoerd Simons <sjoerd.simons@collabora.co.uk> |
clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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#
66746420 |
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22-Dec-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: include downstream muxes into fractional dividers Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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#
dfff24bd |
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18-Dec-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
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#
60ecbd9d |
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11-Aug-2015 |
ZhengShunQian <zhengsq@rock-chips.com> |
clk: rockchip: use rk3288-efuse clock ids Reference the newly added efuse clock-ids in the clock-tree. Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
1d33929e |
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26-Nov-2015 |
Chris Zhong <zyw@rock-chips.com> |
clk: rockchip: switch PLLs to slow mode before reboot for rk3288 We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the problem by switching to slow mode before reboot, just like what we did before suspend. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
a2f4c560 |
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26-Nov-2015 |
Chris Zhong <zyw@rock-chips.com> |
clk: rockchip: add mipidsi clock on rk3288 sclk_mipidsi_24m is the gating of mipi dsi phy. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
751be8f2 |
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16-Nov-2015 |
Zain Wang <zain.wang@rock-chips.com> |
clk: rockchip: set the id for crypto clk Set the newly added id for the crypto clk, so that it can be called in other parts. Signed-off-by: Zain Wang <zain.wang@rock-chips.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
15ee1f7d |
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11-Aug-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pclk_pd_pmu needs to keep running and with the upcoming gpio clock handling this is not always the case anymore. So add it to the list of critical clocks for now. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2bbfe001 |
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21-Jul-2015 |
Douglas Anderson <dianders@chromium.org> |
clk: rockchip: Fix PLL bandwidth In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
4534b111 |
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05-Jul-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: define the inverters of rk3066/rk3188 and rk3288 Both soc series' have inverters on the hsadc and camera interface clock paths. So define them using the newly added inverter type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
10176297 |
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18-Jun-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: fix faulty vip parent name on rk3288 The video input processor (vip) was called camera interface (cif) on older socs which seems to have resulted in a copy'n'paste error when creating the rk3288 camera clocks. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
4791eb61 |
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18-Jun-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
9b030bc9 |
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27-Apr-2015 |
Krzysztof Kozlowski <krzk@kernel.org> |
clk: rockchip: Staticize file-scope declarations Add missing static to local (file-scope only) symbols. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
692d8328 |
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18-Feb-2015 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
clk: don't use __initconst for non-const arrays The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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#
e142a4e9 |
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20-Jan-2015 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288 The pclk supplying the watchdog is controlled via the SGRF register area. Currently we don't have any clock-type handling external clock bits like this one. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
cc643068 |
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18-Dec-2014 |
huang lin <hl@rock-chips.com> |
clk: rockchip: add PVTM clocks on rk3288 Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks: PVTM_CORE and PVTM_GPU. Signed-off-by: Huang Lin <hl@rock-chips.com> Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
f5c3018d |
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13-Nov-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: use the clock ID for usbphy480m_src Use the clock ID for usbphy480m_src so that we can find this clock node in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
7f186025 |
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29-Dec-2014 |
Roger Chen <roger.chen@rock-chips.com> |
GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC modify CRU config for GMAC driver changes since v2: 1. remove SCLK_MAC_PLL Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a7d95000 |
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22-Dec-2014 |
Doug Anderson <dianders@chromium.org> |
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode We've been seeing some crashes at resume time on rk3288-based systems. On some machines they simply never wake up from suspend. Symptoms include: - System clearly got to sleep OK. Power consumption is low, the PWM for the PWM regulator has stopped, and the "global_pwroff" output shows that the system is down. - When system tries to wake up power consumption goes up. - No kernel resume code (which was left in PMU SRAM) ran. We added some basic logging to this code (write to a location in SRAM right at resume time) and didn't see the logging run. It appears that we can fix the problem by slowing down APLL before we suspend. On the system I tested things seemed reliable if I disabled 1.8GHz and 1.7GHz. The Mask ROM itself tries to slow things down (which is why PLLs are in slow mode by the time we get to the kernel), but apparently it is crashing before it even gets there. We'll be super paranoid and not just go down to 1.6GHz but we'll match what the Mask ROM seems to be doing and go into slow mode. We'll also be safe and put all PLLs (not just APLL) into slow mode (well, except DPLL which is needed for SDRAM). We'll even put NPLL into slow mode which the Mask ROM didn't do (not that it's used for much important stuff at early resume time). Note that the old Rockchip reference code did something just like this, though they jammed it into pm.c instead of putting it in the syscore ops of the clock driver. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
9880d427 |
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18-Dec-2014 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: fix rk3288 cpuclk core dividers Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Cc: stable@vger.kernel.org
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#
221dfbae |
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04-Dec-2014 |
Doug Anderson <dianders@chromium.org> |
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks We'd like to be able to set the clock rate of the sclk_uart clocks and actually be able to achieve clock rates greater than 24MHz. To do this we need to be able to pass rate changes upward. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
89bf26cb |
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26-Nov-2014 |
Alexandru M Stan <amstan@chromium.org> |
clk: rockchip: Add support for the mmc clock phases using the framework This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
6d288b16 |
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19-Nov-2014 |
Sonny Rao <sonnyrao@chromium.org> |
clk: rockchip: rk3288 export i2s0_clkout for use in DT This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
a72da7c1 |
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25-Nov-2014 |
Jeff Chen <cym@rock-chips.com> |
clk: rockchip: use clock ID for DMC (memory controller) on rk3288 The DMC clocks need to be turned off at runtime. Use the newly assigned clock IDs to export them. Signed-off-by: Jeff Chen <cym@rock-chips.com> [dianders: split into two patches; adjusted commit msg] Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
dd79c0be |
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20-Nov-2014 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls Add the new flag to gpll and cpll on rk3188 and similar and to gpll, cpll and npll on rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
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#
4f8a7c54 |
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20-Nov-2014 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: add ability to specify pll-specific flags This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
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#
29e94468 |
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13-Nov-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: fix clock select order for rk3288 usbphy480m_src According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 - clk_otgphy0 -> USB PHY OTG - clk_otgphy1 -> USB PHY host0 - clk_otgphy2 -> USB PHY host1 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
01322341 |
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13-Nov-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register According to rk3288 trm, the clk_usbphy480m_gate is located at bit 14 of CRU_CLKGATE5_CON register. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
9aa75e6e |
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12-Nov-2014 |
Dmitry Torokhov <dtor@chromium.org> |
clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled Currently there is no driver owning these clocks and they have to stay up for the system to function properly, so let's mark them as CLK_IGNORE_UNUSED. Without this patch we have trouble with suspend/resume and we have trouble turning the eDP back on if it ever idles off. Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
33aa59c2 |
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07-Nov-2014 |
Chris Zhong <zyw@rock-chips.com> |
clk: rockchip: rk3288: add suspend and resume save and restore some clks, which might be changed in suspend. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
78eaf609 |
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04-Nov-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: disable unused clocks The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure all the clocks are available like default power on state. We have implement the clock manage in most of rockchip drivers, it is time to remove it for power save. Instead we add CLK_IGNORE_UNUSED for some clock nodes which should be on during boot or no module driver in kernel will initialize it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
49ed9ee4 |
|
09-Oct-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: change PLL setting for better clock jitter dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we use 594MHz for clock source of dclk_vop0/1. HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit: TMDS clock(MHz) CTS require jitter (ps) 297 84.2 148.5 168 74.25 336 27 1247 PLL BW and VCO frequency effects the jitter of PLL output clock, clock jitter is better if BW is lower or VCO frequency is higher. If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4), the TMDS Clock jitter is higher than 250ps, which means we can't pass the test when TMDS clock is 297MHz or 148.5MHz. If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), the TMDS Clock jitter is about 60ps and we can pass all test case. So we need this patch to make hdmi si test pass. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
89c107a8 |
|
16-Oct-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: add npll to source of sclk_gpu The possible sources for the rk3288-gpu-clock also include the npll, making it the same list of sources as for uart0. This patch make a common source for uart0 pll src and sclk_gpu, so that gpu can get its clock from npll. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
8f06f5d3 |
|
20-Oct-2014 |
Jianqun <jay.xu@rock-chips.com> |
clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout to select between its two parent without being able influence the core i2s clock. Tested on rk3288 board, suggested by Heiko. Signed-off-by: Jianqun <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
cd9b4609 |
|
09-Oct-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate This patch add 400MHz and 500MHz to clock rate table for rk3288. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
61e309f3 |
|
06-Oct-2014 |
Doug Anderson <dianders@chromium.org> |
clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at bootup. In order for this to have any effect we need its parent (aclk_cpu_pre) to percolate the rate change to _its_ parent (aclk_cpu_src). Add CLK_SET_RATE_PARENT to make this happen. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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#
de7d6c3e |
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08-Oct-2014 |
Sonny Rao <sonnyrao@chromium.org> |
clk: rockchip: fix parent for spdif_8ch_frac on rk3288 The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't exist and looks to be a typo. The TRM also confirms this. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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6f1294b5 |
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19-Aug-2014 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: add restart handler Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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fc69ed70 |
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29-Sep-2014 |
Jianqun <jay.xu@rock-chips.com> |
clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay <music.wav>" Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: Jianqun <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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0e5bdb3f |
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05-Sep-2014 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: switch to using the new cpuclk type for armclk This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
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2b9bceea |
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04-Sep-2014 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: make tightly bound armclk child-clocks read-only Rockchip SoCs contain clocks tightly bound to the armclk, where the best rate / divider is supplied by the vendor after careful measuring. Often this ideal rate may be greater than the current rate. Therefore prevent the ccf from trying to set these dividers itself by setting them to read-only. In the case of the rk3066, this also includes the aclk_cpu, which makes it necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...) into individual definitions for rk3066 and rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
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ee17eb83 |
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01-Sep-2014 |
Jianqun <jay.xu@rock-chips.com> |
clk: rockchip: fix rk3288 pll status register location In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: Jianqun <jay.xu@rock-chips.com> Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
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cd248502 |
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25-Sep-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: add clock node in PD_VIDEO This patch add the clock node in PD_VIDEO Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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89d83e14 |
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25-Sep-2014 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rockchip: use the clock id for nodes init This patch use the new defined clock ID to initial the clock nodes. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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d1a559a1 |
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24-Sep-2014 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: add missing rk3288 npll rate table The npll on rk3288 is exactly the same pll type as the other 4. Yet it was missing the link to the rate table, making rate changes impossible. Change that by setting the table. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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f9c0d140 |
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12-Sep-2014 |
Mark Yao <markyao0591@gmail.com> |
clk: rockchip: rk3288: fix softreset register count The rk3288 actually has 12 softresets, so fix the register count. Signed-off-by: Mark yao <mark.yao@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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2fed71e5 |
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10-Sep-2014 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: also protect hclk_peri as critical The dwc2 usb controller also uses agressive clock gating, which in this case leads to hclk_peri getting disabled and hanging the system. Therefore move it to the critical clocks until we also control that part of the system. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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f4ee3c84 |
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22-Aug-2014 |
Doug Anderson <dianders@chromium.org> |
clk: rockchip: Fix the clocks for i2c1 and i2c2 The clocks for i2c1 and i2c2 are flipped. The clock tree matched the Technical Reference Manual (TRM) but the TRM was wrong. Swap them in the clock tree. This was determined experimentally (by Addy) and confirmed by the Rockchip IC team. Signed-off-by: Doug Anderson <dianders@chromium.org> Reported-by: Addy Ke <addy.ke@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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fe94f974 |
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14-Aug-2014 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: protect critical clocks from getting disabled The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals. Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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b9e4ba54 |
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02-Jul-2014 |
Heiko Stübner <heiko@sntech.de> |
clk: rockchip: add clock controller for rk3288 Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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