| /linux-master/arch/x86/crypto/ |
| H A D | sha1_ni_asm.S | 68 #define E1 %xmm2 define
123 movdqa ABCD, E1
129 sha1nexte MSG1, E1
131 sha1rnds4 $0, E1, ABCD
138 movdqa ABCD, E1
146 sha1nexte MSG3, E1
149 sha1rnds4 $0, E1, ABCD
155 movdqa ABCD, E1
162 sha1nexte MSG1, E1
165 sha1rnds4 $1, E1, ABC
[all...] |
| /linux-master/arch/m68k/fpsp040/ |
| H A D | skeleton.S | 68 bclrb #E1,E_BYTE(%a6)
85 | otherwise clear the E1 exception. The frestore is not really
86 | necessary for E1 exceptions.
89 | bug, if an E1 snan, ovfl, or unfl occurred, and the process was
93 | fix is to check for E1, and the existence of one of snan, ovfl,
108 btstb #E1,E_BYTE(%a6) |test for E1 set
158 bclrb #E1,E_BYTE(%a6)
184 bclrb #E1,E_BYTE(%a6)
210 bclrb #E1,E_BYT
[all...] |
| H A D | gen_except.S | 168 | exception is to set the E1/E3 byte and clr the U flag.
169 | commonE1 does this for E1 exceptions, which are snan,
171 | are inex2 and inex1, and also clears the E1 exception bit
175 bsetb #E1,E_BYTE(%a6) |set E1 flag
183 bclrb #E1,E_BYTE(%a6) |clr E1 from unimp
192 bclrb #E1,E_BYTE(%a6) |clr E1 flag
268 bsetb #E1,E_BYT
[all...] |
| H A D | fpsp.h | 172 .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes)
189 .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte)
190 .set E1,2 | which bit is E1 flag
|
| H A D | util.S | 336 | else E1
435 | If E1, the format is from cmdreg1b{12:10}
446 clrl %d0 |if E1, size is always ext
|
| H A D | x_operr.S | 345 | Since operr is only an E1 exception, there is no need to frestore
|
| H A D | res_func.S | 406 bclrb #E1,E_BYTE(%a6)
761 bclrb #E1,E_BYTE(%a6)
1221 bclrb #E1,E_BYTE(%a6)
1349 bclrb #E1,E_BYTE(%a6)
1455 bclrb #E1,E_BYTE(%a6)
1473 bclrb #E1,E_BYTE(%a6)
|
| H A D | decbin.S | 47 | representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted
|
| H A D | x_snan.S | 115 bclrb #E1,E_BYTE(%a6)
|
| /linux-master/drivers/gpu/drm/i915/ |
| H A D | intel_step.h | 44 func(E1) \
|
| /linux-master/lib/ |
| H A D | locking-selftest.c | 285 static void name##_12(void) { E1(); E2(); } \
286 static void name##_21(void) { E2(); E1(); }
290 static void name##_123(void) { E1(); E2(); E3(); } \
291 static void name##_132(void) { E1(); E3(); E2(); } \
292 static void name##_213(void) { E2(); E1(); E3(); } \
293 static void name##_231(void) { E2(); E3(); E1(); } \
294 static void name##_312(void) { E3(); E1(); E2(); } \
295 static void name##_321(void) { E3(); E2(); E1(); }
793 #define E1() \ macro
828 #undef E1 macro
835 #define E1 macro
861 #undef E1 macro
869 #define E1 macro
906 #undef E1 macro
912 #define E1 macro
954 #undef E1 macro
963 #define E1 macro
1004 #undef E1 macro
1024 #define E1 macro
1068 #undef E1 macro
1076 #define E1 macro
1100 #undef E1 macro
1108 #define E1 macro
1132 #undef E1 macro
1140 #define E1 macro
1164 #undef E1 macro
1172 #define E1 macro
1196 #undef E1 macro
1203 #define E1 macro
1243 #undef E1 macro
1251 #define E1 macro
1291 #undef E1 macro
1307 #define E1 macro
[all...] |
| /linux-master/drivers/net/wan/ |
| H A D | farsync.h | 116 unsigned char framing; /* E1, T1 or J1 */
194 #define E1 6 macro
226 * Constants for T1/E1 configuration
|
| H A D | farsync.c | 1638 if (info->framing == E1)
1830 FST_WRW(card, portConfig[i].lineInterface, E1);
1831 port->hwif = E1;
1869 case E1:
|
| /linux-master/arch/arc/kernel/ |
| H A D | troubleshoot.c | 201 STS_BIT(regs, E2), STS_BIT(regs, E1));
|
| /linux-master/drivers/gpu/drm/amd/display/modules/color/ |
| H A D | color_gamma.c | 974 struct fixed31_32 E1; local
993 compute_pq(input_x, &E1);
1000 if (dc_fixpt_lt(E1, ks))
1001 E2 = E1;
1002 else if (dc_fixpt_le(ks, E1) && dc_fixpt_le(E1, dc_fixpt_one)) {
1004 // t = (E1 - ks) / (1 - ks)
1005 t = dc_fixpt_div(dc_fixpt_sub(E1, ks),
|
| /linux-master/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g5.c | 1333 #define E1 179 macro
1334 SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1335 SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
1336 PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
1337 FUNC_GROUP_DECL(ADC3, E1);
1994 ASPEED_PINCTRL_PIN(E1),
2571 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA
[all...] |
| H A D | pinctrl-aspeed-g6.c | 1450 #define E1 231 macro
1451 SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23),
1453 SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23),
1455 PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER);
1457 FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
1458 FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
1805 ASPEED_PINCTRL_PIN(E1),
2619 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
2620 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
|