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0ec8ae43 |
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20-Sep-2023 |
Joe Wang <joe_wang@aspeedtech.com> |
pinctrl: pinctrl-aspeed-g6: Add more settings for USB2AHP function AST2600 USB2AHP (USB PortA: PCIe EHCI to PHY) function needs to set the register SCUC20[16]. Set it to enable the PCIe EHCI device on PCIe bus. Besides, also add USB2AHP signal expressions into pin declarations. Signed-off-by: Joe Wang <joe_wang@aspeedtech.com> Link: https://lore.kernel.org/r/20230920103332.274151-1-joe_wang@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f8b61bb6 |
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29-Mar-2022 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-5-quic_jaehyoo@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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05ffcd0d |
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29-Mar-2022 |
Jae Hyun Yoo <quic_jaehyoo@quicinc.com> |
pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-3-quic_jaehyoo@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6082be2a |
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29-Mar-2022 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-5-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
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3eef2f48 |
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29-Mar-2022 |
Jae Hyun Yoo <quic_jaehyoo@quicinc.com> |
pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-3-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
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0b971484 |
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24-May-2021 |
Steven Lee <steven_lee@aspeedtech.com> |
pinctrl: pinctrl-aspeed-g6: Add sgpio pinctrl settings AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. Current pinctrl driver only define the first sgpio master and slave interfaces. The second SGPIO master and slave interfaces should be added in pinctrl driver as well. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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333944c7 |
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25-Apr-2021 |
Souptick Joarder <jrdr.linux@gmail.com> |
pinctrl: aspeed: Fix minor documentation error Kernel test robot throws below warning -> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c:2705: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2614: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinctrl-aspeed.c:111: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinmux-aspeed.c:24: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Fix minor documentation error. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Cc: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/1619353584-8196-1-git-send-email-jrdr.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
92ff62a7 |
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16-Dec-2020 |
Billy Tsai <billy_tsai@aspeedtech.com> |
pinctrl: aspeed: g6: Fix PWMG0 pinctrl setting The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from SCU414 to SCU4B4. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20201217024912.3198-1-billy_tsai@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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05c0a8a9 |
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09-Sep-2020 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed-g6: Add bias controls for 1.8V GPIO banks These were skipped in the original patches adding pinconf support for the AST2600. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Cc: Johnny Huang <johnny_huang@aspeedtech.com> Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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13c502c8 |
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30-Jun-2020 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed: Describe the heartbeat function on ball Y23 The default pinmux configuration for Y23 is to route a heartbeat to drive a LED. Previous revisions of the AST2600 datasheet did not include a description of this function. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200701030756.2834657-1-joel@jms.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
15711ba6 |
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01-Dec-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Add AST2600 pinconf support The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
22d69190 |
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01-Dec-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Add support for the AST2600 USB pinmux AST2600 has two USB ports, A, B: Port A supports 4 distinct modes: 1. PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8b99fb9f |
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01-Dec-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux config These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
eb45f211 |
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01-Dec-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed-g6: Fix LPC/eSPI mux configuration Early revisions of the AST2600 datasheet are conflicted about the state of the LPC/eSPI strapping bit (SCU510[6]). Conversations with ASPEED determined that the reference pinmux configuration tables were in error and the SCU documentation contained the correct configuration. Update the driver to reflect the state described in the SCU documentation. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202050110.15340-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d6e7a1a5 |
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07-Oct-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
15505834 |
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07-Oct-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Fix UART13 group pinmux When UART13G1 is set the pinmux configuration in SCU4B8 for UART13G0 should be cleared. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-7-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9979346f |
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07-Oct-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially unclear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, resolve rebase conflicts] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-5-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b178f91f |
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07-Oct-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed-g6: Fix I2C14 SDA description The I2C function the pin participated in was incorrectly named SDA14 which lead to a failure to mux: [ 6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-4-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
377dfcdc |
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07-Oct-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed-g6: Sort pins for sanity Some pins crept in that weren't ordered in the list. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
21b2920f |
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06-Aug-2019 |
Nathan Chancellor <nathan@kernel.org> |
pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter clang errors: drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' with an expression of type 'int (const struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' [-Werror,-Wincompatible-pointer-types] .set = aspeed_g6_sig_expr_set, ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") changed the set function pointer declaration and the g6 one wasn't updated (I assume because it wasn't merged yet). Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Link: https://github.com/ClangBuiltLinux/linux/issues/632 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20190807003037.48457-1-natechancellor@gmail.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2eda1cde |
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10-Jul-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed: Add AST2600 pinmux support The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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