Searched refs:DP_VID_STREAM_CNTL (Results 1 - 19 of 19) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.h51 SRI(DP_VID_STREAM_CNTL, DP, id), \
H A Ddcn30_dio_stream_encoder.h95 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.h52 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h69 SRI(DP_VID_STREAM_CNTL, DP, id), \
102 SRI(DP_VID_STREAM_CNTL, DP, id), \
179 uint32_t DP_VID_STREAM_CNTL; member in struct:dce110_link_enc_registers
H A Ddce_stream_encoder.h91 SRI(DP_VID_STREAM_CNTL, DP, id), \
162 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
164 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
663 uint32_t DP_VID_STREAM_CNTL; member in struct:dce110_stream_enc_registers
H A Ddce_stream_encoder.c915 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
921 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
929 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
936 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
1010 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
H A Ddce_link_encoder.c457 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
509 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c332 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
333 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
378 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c341 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
342 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
367 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
H A Ddcn314_dio_stream_encoder.h96 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c364 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
365 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
390 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
H A Ddcn35_dio_stream_encoder.h95 SRI(DP_VID_STREAM_CNTL, DP, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.c515 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
516 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
547 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c919 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
926 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
934 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
943 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
1026 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
H A Ddcn10_link_encoder.h62 SRI(DP_VID_STREAM_CNTL, DP, id), \
104 uint32_t DP_VID_STREAM_CNTL; member in struct:dcn10_link_enc_registers
H A Ddcn10_stream_encoder.h93 SRI(DP_VID_STREAM_CNTL, DP, id), \
143 uint32_t DP_VID_STREAM_CNTL; member in struct:dcn10_stream_enc_registers
H A Ddcn10_link_encoder.c389 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h126 SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h290 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
326 SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \

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