Searched refs:DPPCLK (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
40 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
41 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
42 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
43 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
44 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
45 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_dccg.h34 DCCG_SRII(DTO_PARAM, DPPCLK, 4)
38 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
39 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_dccg.h34 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
43 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
44 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
45 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
46 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
73 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
74 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
75 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
76 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
77 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
78 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.h38 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
39 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
40 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
41 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
81 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
82 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
83 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
84 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
172 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
173 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
44 DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
45 DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
61 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
62 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
63 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
64 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.h35 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
36 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
37 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
38 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
39 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
40 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
41 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
42 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.h48 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
49 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
50 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
51 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c43 double DPPCLK; member in struct:__anon223
280 double DPPCLK,
319 double DPPCLK[],
368 double DPPCLK[],
415 double DPPCLK[],
918 myPipe->DPPCLK,
969 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
972 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
1881 // DISPCLK and DPPCLK Calculation
2024 v->DPPCLK[
3279 CalculateDynamicMetadataParameters(int MaxInterDCNTileRepeaters, double DPPCLK, double DISPCLK, double DCFClkDeepSleep, double PixelClock, long HTotal, long VBlank, long DynamicMetadataTransmittedBytes, long DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP, double *Tsetup, double *Tdmbf, double *Tdmec, double *Tdmsks) argument
5191 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceBufferSize, double DCFCLK, double ReturnBW, bool GPUVMEnable, unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], unsigned int LBBitPerPixel[], double SwathWidthY[], double SwathWidthC[], double HRatio[], double HRatioChroma[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], double VRatioChroma[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], double DSTXAfterScaler[], double DSTYAfterScaler[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument
5408 CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, int BytePerPixelY[], int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], double ReadBandwidthLuma[], double ReadBandwidthChroma[], int ReturnBusWidth, double *DCFCLKDeepSleep) argument
5547 CalculatePixelDeliveryTimes( unsigned int NumberOfActivePlanes, double VRatio[], double VRatioChroma[], double VRatioPrefetchY[], double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][2], unsigned int CursorBPP[][2], unsigned int BlockWidth256BytesY[], unsigned int BlockHeight256BytesY[], unsigned int BlockWidth256BytesC[], unsigned int BlockHeight256BytesC[], double DisplayPipeLineDeliveryTimeLuma[], double DisplayPipeLineDeliveryTimeChroma[], double DisplayPipeLineDeliveryTimeLumaPrefetch[], double DisplayPipeLineDeliveryTimeChromaPrefetch[], double DisplayPipeRequestDeliveryTimeLuma[], double DisplayPipeRequestDeliveryTimeChroma[], double DisplayPipeRequestDeliveryTimeLumaPrefetch[], double DisplayPipeRequestDeliveryTimeChromaPrefetch[], double CursorRequestDeliveryTime[], double CursorRequestDeliveryTimePrefetch[]) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c42 double DPPCLK; member in struct:__anon436
312 double DPPCLK[],
354 double DPPCLK[],
398 double DPPCLK[],
737 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
740 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK
756 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK);
757 *VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime)
761 150.0 / myPipe->DPPCLK,
762 TotalRepeaterDelayTime + 20.0 / myPipe->DCFCLKDeepSleep + 10.0 / myPipe->DPPCLK)
5242 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], unsigned int SwathHeightY[], double ReadBandwidthPlaneLuma[], unsigned int SwathHeightC[], double ReadBandwidthPlaneChroma[], unsigned int LBBitPerPixel[], double SwathWidthY[], double HRatio[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument
5526 CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, double BytePerPixelDETY[], double BytePerPixelDETC[], double VRatio[], double SwathWidthY[], int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], double *DCFCLKDeepSleep) argument
5732 CalculatePixelDeliveryTimes( unsigned int NumberOfActivePlanes, double VRatio[], double VRatioPrefetchY[], double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], double BytePerPixelDETC[], enum scan_direction_class SourceScan[], unsigned int BlockWidth256BytesY[], unsigned int BlockHeight256BytesY[], unsigned int BlockWidth256BytesC[], unsigned int BlockHeight256BytesC[], double DisplayPipeLineDeliveryTimeLuma[], double DisplayPipeLineDeliveryTimeChroma[], double DisplayPipeLineDeliveryTimeLumaPrefetch[], double DisplayPipeLineDeliveryTimeChromaPrefetch[], double DisplayPipeRequestDeliveryTimeLuma[], double DisplayPipeRequestDeliveryTimeChroma[], double DisplayPipeRequestDeliveryTimeLumaPrefetch[], double DisplayPipeRequestDeliveryTimeChromaPrefetch[]) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c63 double DPPCLK; member in struct:__anon441
274 double DPPCLK,
333 double DPPCLK[],
379 double DPPCLK[],
927 myPipe->DPPCLK,
991 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
994 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
999 dml_print("DML::%s: DPPCLK: %f\n", __func__, myPipe->DPPCLK);
2031 // DISPCLK and DPPCLK Calculatio
3413 CalculateVupdateAndDynamicMetadataParameters( int MaxInterDCNTileRepeaters, double DPPCLK, double DISPCLK, double DCFClkDeepSleep, double PixelClock, int HTotal, int VBlank, int DynamicMetadataTransmittedBytes, int DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP, double *TSetup, double *Tdmbf, double *Tdmec, double *Tdmsks, int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) argument
5760 CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, int BytePerPixelY[], int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], double ReadBandwidthLuma[], double ReadBandwidthChroma[], int ReturnBusWidth, double *DCFCLKDeepSleep) argument
5899 CalculatePixelDeliveryTimes( unsigned int NumberOfActivePlanes, double VRatio[], double VRatioChroma[], double VRatioPrefetchY[], double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], unsigned int BlockWidth256BytesY[], unsigned int BlockHeight256BytesY[], unsigned int BlockWidth256BytesC[], unsigned int BlockHeight256BytesC[], double DisplayPipeLineDeliveryTimeLuma[], double DisplayPipeLineDeliveryTimeChroma[], double DisplayPipeLineDeliveryTimeLumaPrefetch[], double DisplayPipeLineDeliveryTimeChromaPrefetch[], double DisplayPipeRequestDeliveryTimeLuma[], double DisplayPipeRequestDeliveryTimeChroma[], double DisplayPipeRequestDeliveryTimeLumaPrefetch[], double DisplayPipeRequestDeliveryTimeChromaPrefetch[], double CursorRequestDeliveryTime[], double CursorRequestDeliveryTimePrefetch[]) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c64 double DPPCLK; member in struct:__anon392
286 double DPPCLK,
345 double DPPCLK[],
391 double DPPCLK[],
948 myPipe->DPPCLK,
1012 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
1015 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
1020 dml_print("DML::%s: DPPCLK: %f\n", __func__, myPipe->DPPCLK);
2052 // DISPCLK and DPPCLK Calculatio
3522 CalculateVupdateAndDynamicMetadataParameters( int MaxInterDCNTileRepeaters, double DPPCLK, double DISPCLK, double DCFClkDeepSleep, double PixelClock, int HTotal, int VBlank, int DynamicMetadataTransmittedBytes, int DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP, double *TSetup, double *Tdmbf, double *Tdmec, double *Tdmsks, int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) argument
5857 CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, int BytePerPixelY[], int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], double ReadBandwidthLuma[], double ReadBandwidthChroma[], int ReturnBusWidth, double *DCFCLKDeepSleep) argument
5996 CalculatePixelDeliveryTimes( unsigned int NumberOfActivePlanes, double VRatio[], double VRatioChroma[], double VRatioPrefetchY[], double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], unsigned int DPPPerPlane[], double HRatio[], double HRatioChroma[], double PixelClock[], double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], unsigned int CursorBPP[][DC__NUM_CURSOR__MAX], unsigned int BlockWidth256BytesY[], unsigned int BlockHeight256BytesY[], unsigned int BlockWidth256BytesC[], unsigned int BlockHeight256BytesC[], double DisplayPipeLineDeliveryTimeLuma[], double DisplayPipeLineDeliveryTimeChroma[], double DisplayPipeLineDeliveryTimeLumaPrefetch[], double DisplayPipeLineDeliveryTimeChromaPrefetch[], double DisplayPipeRequestDeliveryTimeLuma[], double DisplayPipeRequestDeliveryTimeChroma[], double DisplayPipeRequestDeliveryTimeLumaPrefetch[], double DisplayPipeRequestDeliveryTimeChromaPrefetch[], double CursorRequestDeliveryTime[], double CursorRequestDeliveryTimePrefetch[]) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20v2.c64 double DPPCLK,
93 double DPPCLK,
471 double DPPCLK,
520 if (DPPCLK == 0.0 || DISPCLK == 0.0)
523 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
543 double DPPCLK,
610 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
611 *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime)
615 150.0 / DPPCLK,
616 TotalRepeaterDelayTime + 20.0 / DCFCLKDeepSleep + 10.0 / DPPCLK)
463 CalculateDelayAfterScaler( struct display_mode_lib *mode_lib, double ReturnBW, double ReadBandwidthPlaneLuma, double ReadBandwidthPlaneChroma, double TotalDataReadBandwidth, double DisplayPipeLineDeliveryTimeLuma, double DisplayPipeLineDeliveryTimeChroma, double DPPCLK, double DISPCLK, double PixelClock, unsigned int DSCDelay, unsigned int DPPPerPlane, bool ScalerEnabled, unsigned int NumberOfCursors, double DPPCLKDelaySubtotal, double DPPCLKDelaySCL, double DPPCLKDelaySCLLBOnly, double DPPCLKDelayCNVCFormater, double DPPCLKDelayCNVCCursor, double DISPCLKDelaySubtotal, unsigned int ScalerRecoutWidth, enum output_format_class OutputFormat, unsigned int HTotal, unsigned int SwathWidthSingleDPPY, double BytePerPixelDETY, double BytePerPixelDETC, unsigned int SwathHeightY, unsigned int SwathHeightC, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, double *DSTXAfterScaler, double *DSTYAfterScaler ) argument
541 CalculatePrefetchSchedule( struct display_mode_lib *mode_lib, double DPPCLK, double DISPCLK, double PixelClock, double DCFCLKDeepSleep, unsigned int DPPPerPlane, unsigned int NumberOfCursors, unsigned int VBlank, unsigned int HTotal, unsigned int MaxInterDCNTileRepeaters, unsigned int VStartup, unsigned int PageTableLevels, bool GPUVMEnable, bool DynamicMetadataEnable, unsigned int DynamicMetadataLinesBeforeActiveRequired, unsigned int DynamicMetadataTransmittedBytes, bool DCCEnable, double UrgentLatencyPixelDataOnly, double UrgentExtraLatency, double TCalc, unsigned int PDEAndMetaPTEBytesFrame, unsigned int MetaRowByte, unsigned int PixelPTEBytesPerRow, double PrefetchSourceLinesY, unsigned int SwathWidthY, double BytePerPixelDETY, double VInitPreFillY, unsigned int MaxNumSwathY, double PrefetchSourceLinesC, double BytePerPixelDETC, double VInitPreFillC, unsigned int MaxNumSwathC, unsigned int SwathHeightY, unsigned int SwathHeightC, double TWait, bool XFCEnabled, double XFCRemoteSurfaceFlipDelay, bool InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP, double DSTXAfterScaler, double DSTYAfterScaler, double *DestinationLinesForPrefetch, double *PrefetchBandwidth, double *DestinationLinesToRequestVMInVBlank, double *DestinationLinesToRequestRowInVBlank, double *VRatioPrefetchY, double *VRatioPrefetchC, double *RequiredPrefetchPixDataBW, double *Tno_bw, unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) argument
[all...]
H A Ddisplay_mode_vba_20.c58 double DPPCLK,
441 double DPPCLK,
528 if (DPPCLK == 0.0 || DISPCLK == 0.0)
531 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
547 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
548 *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime)
552 150.0 / DPPCLK,
553 TotalRepeaterDelayTime + 20.0 / DCFCLKDeepSleep + 10.0 / DPPCLK)
1095 // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
1433 / mode_lib->vba.DPPCLK[
439 CalculatePrefetchSchedule( struct display_mode_lib *mode_lib, double DPPCLK, double DISPCLK, double PixelClock, double DCFCLKDeepSleep, unsigned int DSCDelay, unsigned int DPPPerPlane, bool ScalerEnabled, unsigned int NumberOfCursors, double DPPCLKDelaySubtotal, double DPPCLKDelaySCL, double DPPCLKDelaySCLLBOnly, double DPPCLKDelayCNVCFormater, double DPPCLKDelayCNVCCursor, double DISPCLKDelaySubtotal, unsigned int ScalerRecoutWidth, enum output_format_class OutputFormat, unsigned int VBlank, unsigned int HTotal, unsigned int MaxInterDCNTileRepeaters, unsigned int VStartup, unsigned int PageTableLevels, bool GPUVMEnable, bool DynamicMetadataEnable, unsigned int DynamicMetadataLinesBeforeActiveRequired, unsigned int DynamicMetadataTransmittedBytes, bool DCCEnable, double UrgentLatencyPixelDataOnly, double UrgentExtraLatency, double TCalc, unsigned int PDEAndMetaPTEBytesFrame, unsigned int MetaRowByte, unsigned int PixelPTEBytesPerRow, double PrefetchSourceLinesY, unsigned int SwathWidthY, double BytePerPixelDETY, double VInitPreFillY, unsigned int MaxNumSwathY, double PrefetchSourceLinesC, double BytePerPixelDETC, double VInitPreFillC, unsigned int MaxNumSwathC, unsigned int SwathHeightY, unsigned int SwathHeightC, double TWait, bool XFCEnabled, double XFCRemoteSurfaceFlipDelay, bool InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP, double *DSTXAfterScaler, double *DSTYAfterScaler, double *DestinationLinesForPrefetch, double *PrefetchBandwidth, double *DestinationLinesToRequestVMInVBlank, double *DestinationLinesToRequestRowInVBlank, double *VRatioPrefetchY, double *VRatioPrefetchC, double *RequiredPrefetchPixDataBW, unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata, double *Tno_bw, unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h1226 SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
1227 DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
1228 DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c707 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz;
1105 mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
1107 mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
H A Ddisplay_mode_vba.h951 double DPPCLK[DC__NUM_DPP__MAX]; member in struct:vba_vars_st
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c84 // DISPCLK and DPPCLK Calculation
138 &v->GlobalDPPCLK, v->DPPCLK);
141 v->DPPCLK_calculated[k] = v->DPPCLK[k];
326 mode_lib->vba.DPPCLK,
763 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
1265 mode_lib->vba.DPPCLK,
2226 //DISPCLK/DPPCLK

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