1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DCN301_DCCG_H__
27#define __DCN301_DCCG_H__
28
29#include "dcn20/dcn20_dccg.h"
30
31#define DCCG_REG_LIST_DCN301() \
32	SR(DPPCLK_DTO_CTRL),\
33	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
37	SR(REFCLK_CNTL)
38
39#define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
40	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
41	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
42	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
43	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
44	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
45	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
46	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
47	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
48	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
49	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
50	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
51	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
52
53struct dccg *dccg301_create(
54	struct dc_context *ctx,
55	const struct dccg_registers *regs,
56	const struct dccg_shift *dccg_shift,
57	const struct dccg_mask *dccg_mask);
58
59struct dccg *dccg301_create(
60	struct dc_context *ctx,
61	const struct dccg_registers *regs,
62	const struct dccg_shift *dccg_shift,
63	const struct dccg_mask *dccg_mask);
64
65#endif //__DCN301_DCCG_H__
66