Searched refs:DPLL_VGA_MODE_DIS (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1006 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1098 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1428 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1454 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1845 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
2187 DPLL_VGA_MODE_DIS) == 0);
2240 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2258 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2288 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
H A Dintel_display_power_well.c1201 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
H A Dintel_display.c8160 DPLL_VGA_MODE_DIS |
8189 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8239 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
/linux-master/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
665 dpll = DPLL_VGA_MODE_DIS;
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
H A Dpsb_intel_display.c158 dpll = DPLL_VGA_MODE_DIS;
H A Doaktrail_crtc.c527 dpll |= DPLL_VGA_MODE_DIS;
H A Dpsb_intel_reg.h232 #define DPLL_VGA_MODE_DIS (1 << 28) macro
/linux-master/drivers/gpu/drm/i915/
H A Di915_reg.h691 #define DPLL_VGA_MODE_DIS (1 << 28) macro

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