Searched refs:DCN_BASE__INST0_SEG4 (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn315.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Ddmub_dcn316.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Ddmub_dcn314.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c49 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Dhw_translate_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-master/drivers/gpu/drm/amd/include/
H A Dnavi10_ip_offset.h271 #define DCN_BASE__INST0_SEG4 0 macro
H A Dyellow_carp_offset.h389 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Drenoir_ip_offset.h1371 #define DCN_BASE__INST0_SEG4 0 macro
H A Dvega10_ip_offset.h307 #define DCN_BASE__INST0_SEG4 0 macro
H A Dsienna_cichlid_ip_offset.h372 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Dbeige_goby_ip_offset.h443 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Ddimgrey_cavefish_ip_offset.h365 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
H A Dvangogh_ip_offset.h454 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c100 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c98 #define DCN_BASE__INST0_SEG4 0x02403C00 macro

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