112657Skvn/* 212657Skvn * Copyright 2021 Advanced Micro Devices, Inc. 312657Skvn * 412657Skvn * Permission is hereby granted, free of charge, to any person obtaining a 512657Skvn * copy of this software and associated documentation files (the "Software"), 612657Skvn * to deal in the Software without restriction, including without limitation 712657Skvn * the rights to use, copy, modify, merge, publish, distribute, sublicense, 812657Skvn * and/or sell copies of the Software, and to permit persons to whom the 912657Skvn * Software is furnished to do so, subject to the following conditions: 1012657Skvn * 1112657Skvn * The above copyright notice and this permission notice shall be included in 1212657Skvn * all copies or substantial portions of the Software. 1312657Skvn * 1412657Skvn * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1512657Skvn * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1612657Skvn * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1712657Skvn * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1812657Skvn * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1912657Skvn * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2012657Skvn * OTHER DEALINGS IN THE SOFTWARE. 2112657Skvn * 2212657Skvn * Authors: AMD 2312657Skvn * 2412657Skvn */ 2512657Skvn#include "dm_services.h" 2612657Skvn#include "include/gpio_types.h" 2712657Skvn#include "../hw_factory.h" 2812657Skvn 2912657Skvn 3012657Skvn#include "../hw_gpio.h" 3112657Skvn#include "../hw_ddc.h" 3212657Skvn#include "../hw_hpd.h" 3312657Skvn#include "../hw_generic.h" 3412657Skvn 3512657Skvn#include "hw_factory_dcn315.h" 3612657Skvn 3712657Skvn#include "dcn/dcn_3_1_5_offset.h" 3812657Skvn#include "dcn/dcn_3_1_5_sh_mask.h" 3912657Skvn 4012657Skvn#include "reg_helper.h" 4112657Skvn#include "../hpd_regs.h" 4212657Skvn/* begin ********************* 4312657Skvn * macros to expend register list macro defined in HW object header file */ 4412657Skvn 4512657Skvn#define DCN_BASE__INST0_SEG0 0x00000012 4612657Skvn#define DCN_BASE__INST0_SEG1 0x000000C0 4712657Skvn#define DCN_BASE__INST0_SEG2 0x000034C0 4812657Skvn#define DCN_BASE__INST0_SEG3 0x00009000 4912657Skvn#define DCN_BASE__INST0_SEG4 0x02403C00 5012657Skvn#define DCN_BASE__INST0_SEG5 0 5112657Skvn 5212657Skvn/* DCN */ 5312657Skvn#define block HPD 5412657Skvn#define reg_num 0 5512657Skvn 5612657Skvn#undef BASE_INNER 5712657Skvn#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 5812657Skvn 5912657Skvn#define BASE(seg) BASE_INNER(seg) 6012657Skvn 6112657Skvn 6212657Skvn 6312657Skvn#define REG(reg_name)\ 6412657Skvn BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name 6512657Skvn 6612657Skvn#define SF_HPD(reg_name, field_name, post_fix)\ 6712657Skvn .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 6812657Skvn 6912657Skvn#define REGI(reg_name, block, id)\ 7012657Skvn BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 7112657Skvn reg ## block ## id ## _ ## reg_name 7212657Skvn 7312657Skvn#define SF(reg_name, field_name, post_fix)\ 7412657Skvn .field_name = reg_name ## __ ## field_name ## post_fix 7512657Skvn 7612657Skvn/* macros to expend register list macro defined in HW object header file 7712657Skvn * end *********************/ 7812657Skvn 7912657Skvn 8012657Skvn 8112657Skvn#define hpd_regs(id) \ 8213491Sdnsimon{\ 8313491Sdnsimon HPD_REG_LIST(id)\ 8413491Sdnsimon} 8513491Sdnsimon 8613491Sdnsimonstatic const struct hpd_registers hpd_regs[] = { 8712657Skvn hpd_regs(0), 8813491Sdnsimon hpd_regs(1), 8913491Sdnsimon hpd_regs(2), 9013491Sdnsimon hpd_regs(3), 9113491Sdnsimon hpd_regs(4), 9213491Sdnsimon}; 9312657Skvn 9412657Skvnstatic const struct hpd_sh_mask hpd_shift = { 9512657Skvn HPD_MASK_SH_LIST(__SHIFT) 9612657Skvn}; 9712657Skvn 9812657Skvnstatic const struct hpd_sh_mask hpd_mask = { 9912657Skvn HPD_MASK_SH_LIST(_MASK) 10012657Skvn}; 10112657Skvn 10212657Skvn#include "../ddc_regs.h" 10312657Skvn 10412657Skvn /* set field name */ 10512657Skvn#define SF_DDC(reg_name, field_name, post_fix)\ 10612657Skvn .field_name = reg_name ## __ ## field_name ## post_fix 10712657Skvn 10812657Skvnstatic const struct ddc_registers ddc_data_regs_dcn[] = { 10912657Skvn ddc_data_regs_dcn2(1), 11012657Skvn ddc_data_regs_dcn2(2), 11112657Skvn ddc_data_regs_dcn2(3), 11212657Skvn ddc_data_regs_dcn2(4), 11312657Skvn ddc_data_regs_dcn2(5), 11412657Skvn { 11512657Skvn DDC_GPIO_VGA_REG_LIST(DATA), 11612657Skvn .ddc_setup = 0, 11712657Skvn .phy_aux_cntl = 0, 11812657Skvn .dc_gpio_aux_ctrl_5 = 0 11912657Skvn } 12012657Skvn}; 12112657Skvn 12212657Skvnstatic const struct ddc_registers ddc_clk_regs_dcn[] = { 12312657Skvn ddc_clk_regs_dcn2(1), 12412657Skvn ddc_clk_regs_dcn2(2), 12512657Skvn ddc_clk_regs_dcn2(3), 12612657Skvn ddc_clk_regs_dcn2(4), 12712657Skvn ddc_clk_regs_dcn2(5), 12812657Skvn { 12912657Skvn DDC_GPIO_VGA_REG_LIST(CLK), 13012657Skvn .ddc_setup = 0, 13112657Skvn .phy_aux_cntl = 0, 13212657Skvn .dc_gpio_aux_ctrl_5 = 0 13312657Skvn } 13412657Skvn}; 13512657Skvn 13612657Skvnstatic const struct ddc_sh_mask ddc_shift[] = { 13712657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), 13812657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), 13912657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), 14012657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), 14112657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), 14212657Skvn DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) 14312657Skvn}; 14412657Skvn 14512657Skvnstatic const struct ddc_sh_mask ddc_mask[] = { 14612657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 1), 14712657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 2), 14812657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 3), 14912657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 4), 15012657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 5), 15112657Skvn DDC_MASK_SH_LIST_DCN2(_MASK, 6) 15212657Skvn}; 15312657Skvn 15412657Skvn#include "../generic_regs.h" 15512657Skvn 15612657Skvn/* set field name */ 15712657Skvn#define SF_GENERIC(reg_name, field_name, post_fix)\ 15812657Skvn .field_name = reg_name ## __ ## field_name ## post_fix 15912657Skvn 16012657Skvn#define generic_regs(id) \ 16112657Skvn{\ 16212657Skvn GENERIC_REG_LIST(id)\ 16312657Skvn} 16412657Skvn 16512657Skvnstatic const struct generic_registers generic_regs[] = { 16612657Skvn generic_regs(A), 16712657Skvn generic_regs(B), 16812657Skvn}; 16912657Skvn 17012657Skvnstatic const struct generic_sh_mask generic_shift[] = { 17112657Skvn GENERIC_MASK_SH_LIST(__SHIFT, A), 17212657Skvn GENERIC_MASK_SH_LIST(__SHIFT, B), 17312657Skvn}; 17412657Skvn 17512657Skvnstatic const struct generic_sh_mask generic_mask[] = { 17612657Skvn GENERIC_MASK_SH_LIST(_MASK, A), 17712657Skvn GENERIC_MASK_SH_LIST(_MASK, B), 17812657Skvn}; 17912657Skvn 18012657Skvnstatic void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) 18112657Skvn{ 18212657Skvn struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); 18312657Skvn 18412657Skvn generic->regs = &generic_regs[en]; 18512657Skvn generic->shifts = &generic_shift[en]; 18612657Skvn generic->masks = &generic_mask[en]; 18712657Skvn generic->base.regs = &generic_regs[en].gpio; 18812657Skvn} 18912657Skvn 19012657Skvnstatic void define_ddc_registers( 19112657Skvn struct hw_gpio_pin *pin, 19212657Skvn uint32_t en) 19312657Skvn{ 19412657Skvn struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); 19512657Skvn 19612657Skvn switch (pin->id) { 19712657Skvn case GPIO_ID_DDC_DATA: 19812657Skvn ddc->regs = &ddc_data_regs_dcn[en]; 19912657Skvn ddc->base.regs = &ddc_data_regs_dcn[en].gpio; 20012657Skvn break; 20112657Skvn case GPIO_ID_DDC_CLOCK: 20212657Skvn ddc->regs = &ddc_clk_regs_dcn[en]; 20312657Skvn ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; 20412657Skvn break; 20512657Skvn default: 20612657Skvn ASSERT_CRITICAL(false); 20712657Skvn return; 20812657Skvn } 20912657Skvn 21012657Skvn ddc->shifts = &ddc_shift[en]; 21112657Skvn ddc->masks = &ddc_mask[en]; 21212657Skvn 21312657Skvn} 21412657Skvn 21512657Skvnstatic void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) 21612657Skvn{ 21712657Skvn struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); 21812657Skvn 21912657Skvn hpd->regs = &hpd_regs[en]; 22012657Skvn hpd->shifts = &hpd_shift; 22112657Skvn hpd->masks = &hpd_mask; 22212657Skvn hpd->base.regs = &hpd_regs[en].gpio; 22312657Skvn} 22412657Skvn 22512657Skvn 22612657Skvn/* fucntion table */ 22713105Sysuenagastatic const struct hw_factory_funcs funcs = { 22813105Sysuenaga .init_ddc_data = dal_hw_ddc_init, 22912657Skvn .init_generic = dal_hw_generic_init, 23012657Skvn .init_hpd = dal_hw_hpd_init, 23112657Skvn .get_ddc_pin = dal_hw_ddc_get_pin, 23212657Skvn .get_hpd_pin = dal_hw_hpd_get_pin, 23312657Skvn .get_generic_pin = dal_hw_generic_get_pin, 23412657Skvn .define_hpd_registers = define_hpd_registers, 23512657Skvn .define_ddc_registers = define_ddc_registers, 23612657Skvn .define_generic_registers = define_generic_registers 23712657Skvn}; 23812657Skvn/* 23912657Skvn * dal_hw_factory_dcn10_init 24012657Skvn * 24112657Skvn * @brief 24212657Skvn * Initialize HW factory function pointers and pin info 24312657Skvn * 24412657Skvn * @param 24512657Skvn * struct hw_factory *factory - [out] struct of function pointers 24612657Skvn */ 24712657Skvnvoid dal_hw_factory_dcn315_init(struct hw_factory *factory) 24812657Skvn{ 24912657Skvn /*TODO check ASIC CAPs*/ 25012657Skvn factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; 25112657Skvn factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; 25212657Skvn factory->number_of_pins[GPIO_ID_GENERIC] = 4; 25312657Skvn factory->number_of_pins[GPIO_ID_HPD] = 6; 25412657Skvn factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; 25512657Skvn factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; 25612657Skvn factory->number_of_pins[GPIO_ID_SYNC] = 0; 25712657Skvn factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ 25812657Skvn 25912657Skvn factory->funcs = &funcs; 26012657Skvn} 26112657Skvn