Searched refs:DCCG_GATE_DISABLE_CNTL (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h167 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.h228 DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h198 SR(DCCG_GATE_DISABLE_CNTL), \
423 SR(DCCG_GATE_DISABLE_CNTL), \
635 uint32_t DCCG_GATE_DISABLE_CNTL; member in struct:dce_hwseq_registers
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c363 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h379 uint32_t DCCG_GATE_DISABLE_CNTL; member in struct:dccg_registers
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c151 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
308 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c249 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c781 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c692 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c683 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c680 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c927 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c686 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c535 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c532 SR(DCCG_GATE_DISABLE_CNTL), \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1663 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

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