Searched refs:DCC (Results 1 - 9 of 9) sorted by relevance
| /linux-master/arch/arm/include/debug/ |
| H A D | icedcc.S | 8 @@ debug using ARM EmbeddedICE DCC channel
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| H A D | tegra.S | 85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
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| /linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 169 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
257 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
368 AMD_FMT_MOD_SET(DCC, 1) |
377 AMD_FMT_MOD_SET(DCC, 1) |
423 * No _D DCC swizzles yet because we only allow 32bpp, which
433 AMD_FMT_MOD_SET(DCC, 1) |
444 AMD_FMT_MOD_SET(DCC, 1) |
455 AMD_FMT_MOD_SET(DCC, 1) |
469 AMD_FMT_MOD_SET(DCC, 1) |
524 AMD_FMT_MOD_SET(DCC,
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| /linux-master/drivers/gpu/drm/i915/ |
| H A D | intel_mchbar_regs.h | 36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) macro
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| H A D | i915_debugfs.c | 360 intel_uncore_read(uncore, DCC));
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_display.c | 662 if (AMD_FMT_MOD_GET(DCC, modifier))
672 * Tries to extract the renderable DCC offset from the opaque metadata attached
853 modifier |= AMD_FMT_MOD_SET(DCC, 1) |
865 * info on the renderable DCC buffer. Luckily the opaque metadata contains
868 * userspace driver that gets it doesn't have to juggle around another DCC
1080 if (AMD_FMT_MOD_GET(DCC, modifier)) {
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| /linux-master/drivers/atm/ |
| H A D | he.h | 657 #define DCC 0x807cc macro
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| H A D | he.c | 1407 he_writel(he_dev, 0x0, DCC);
2727 dcc += he_readl(he_dev, DCC);
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| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.c | 668 u32 dcc = intel_uncore_read(uncore, DCC);
672 * determined by DCC. For single-channel, neither the CPU
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