1/* 2 3 he.h 4 5 ForeRunnerHE ATM Adapter driver for ATM on Linux 6 Copyright (C) 1999-2001 Naval Research Laboratory 7 8 This library is free software; you can redistribute it and/or 9 modify it under the terms of the GNU Lesser General Public 10 License as published by the Free Software Foundation; either 11 version 2.1 of the License, or (at your option) any later version. 12 13 This library is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 Lesser General Public License for more details. 17 18 You should have received a copy of the GNU Lesser General Public 19 License along with this library; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 22*/ 23 24/* 25 26 he.h 27 28 ForeRunnerHE ATM Adapter driver for ATM on Linux 29 Copyright (C) 1999-2000 Naval Research Laboratory 30 31 Permission to use, copy, modify and distribute this software and its 32 documentation is hereby granted, provided that both the copyright 33 notice and this permission notice appear in all copies of the software, 34 derivative works or modified versions, and any portions thereof, and 35 that both notices appear in supporting documentation. 36 37 NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND 38 DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER 39 RESULTING FROM THE USE OF THIS SOFTWARE. 40 41 */ 42 43#ifndef _HE_H_ 44#define _HE_H_ 45 46#define DEV_LABEL "he" 47 48#define CONFIG_DEFAULT_VCIBITS 12 49#define CONFIG_DEFAULT_VPIBITS 0 50 51#define CONFIG_IRQ_SIZE 128 52#define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2) 53 54#define CONFIG_TPDRQ_SIZE 512 55#define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) 56 57#define CONFIG_RBRQ_SIZE 512 58#define CONFIG_RBRQ_THRESH 400 59#define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) 60 61#define CONFIG_TBRQ_SIZE 512 62#define CONFIG_TBRQ_THRESH 400 63#define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) 64 65#define CONFIG_RBPL_SIZE 512 66#define CONFIG_RBPL_THRESH 64 67#define CONFIG_RBPL_BUFSIZE 4096 68#define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) 69 70/* 5.1.3 initialize connection memory */ 71 72#define CONFIG_RSRA 0x00000 73#define CONFIG_RCMLBM 0x08000 74#define CONFIG_RCMABR 0x0d800 75#define CONFIG_RSRB 0x0e000 76 77#define CONFIG_TSRA 0x00000 78#define CONFIG_TSRB 0x08000 79#define CONFIG_TSRC 0x0c000 80#define CONFIG_TSRD 0x0e000 81#define CONFIG_TMABR 0x0f000 82#define CONFIG_TPDBA 0x10000 83 84#define HE_MAXCIDBITS 12 85 86/* 2.9.3.3 interrupt encodings */ 87 88struct he_irq { 89 volatile u32 isw; 90}; 91 92#define IRQ_ALIGNMENT 0x1000 93 94#define NEXT_ENTRY(base, tail, mask) \ 95 (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) 96 97#define ITYPE_INVALID 0xffffffff 98#define ITYPE_TBRQ_THRESH (0<<3) 99#define ITYPE_TPD_COMPLETE (1<<3) 100#define ITYPE_RBPS_THRESH (2<<3) 101#define ITYPE_RBPL_THRESH (3<<3) 102#define ITYPE_RBRQ_THRESH (4<<3) 103#define ITYPE_RBRQ_TIMER (5<<3) 104#define ITYPE_PHY (6<<3) 105#define ITYPE_OTHER 0x80 106#define ITYPE_PARITY 0x81 107#define ITYPE_ABORT 0x82 108 109#define ITYPE_GROUP(x) (x & 0x7) 110#define ITYPE_TYPE(x) (x & 0xf8) 111 112#define HE_NUM_GROUPS 8 113 114/* 2.1.4 transmit packet descriptor */ 115 116struct he_tpd { 117 118 /* read by the adapter */ 119 120 volatile u32 status; 121 volatile u32 reserved; 122 123#define TPD_MAXIOV 3 124 struct { 125 u32 addr, len; 126 } iovec[TPD_MAXIOV]; 127 128#define address0 iovec[0].addr 129#define length0 iovec[0].len 130 131 /* linux-atm extensions */ 132 133 struct sk_buff *skb; 134 struct atm_vcc *vcc; 135 136 struct list_head entry; 137}; 138 139#define TPD_ALIGNMENT 64 140#define TPD_LEN_MASK 0xffff 141 142#define TPD_ADDR_SHIFT 6 143#define TPD_MASK 0xffffffc0 144#define TPD_ADDR(x) ((x) & TPD_MASK) 145#define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) 146 147 148/* table 2.3 transmit buffer return elements */ 149 150struct he_tbrq { 151 volatile u32 tbre; 152}; 153 154#define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE 155 156#define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0) 157#define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3)) 158#define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1)) 159 160/* table 2.21 receive buffer return queue element field organization */ 161 162struct he_rbrq { 163 volatile u32 addr; 164 volatile u32 cidlen; 165}; 166 167#define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE 168 169#define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0) 170#define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5)) 171#define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4)) 172#define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3)) 173#define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2)) 174#define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1)) 175#define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1) 176#define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff) 177#define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff) 178 179/* figure 2.3 transmit packet descriptor ready queue */ 180 181struct he_tpdrq { 182 volatile u32 tpd; 183 volatile u32 cid; 184}; 185 186#define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE 187 188/* table 2.30 host status page detail */ 189 190#define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */ 191 192struct he_hsp { 193 struct he_hsp_entry { 194 volatile u32 tbrq_tail; 195 volatile u32 reserved1[15]; 196 volatile u32 rbrq_tail; 197 volatile u32 reserved2[15]; 198 } group[HE_NUM_GROUPS]; 199}; 200 201/* 202 * figure 2.9 receive buffer pools 203 * 204 * since a virtual address might be more than 32 bits, we store an index 205 * in the virt member of he_rbp. NOTE: the lower six bits in the rbrq 206 * addr member are used for buffer status further limiting us to 26 bits. 207 */ 208 209struct he_rbp { 210 volatile u32 phys; 211 volatile u32 idx; /* virt */ 212}; 213 214#define RBP_IDX_OFFSET 6 215 216/* 217 * the he dma engine will try to hold an extra 16 buffers in its local 218 * caches. and add a couple buffers for safety. 219 */ 220 221#define RBPL_TABLE_SIZE (CONFIG_RBPL_SIZE + 16 + 2) 222 223struct he_buff { 224 struct list_head entry; 225 dma_addr_t mapping; 226 unsigned long len; 227 u8 data[]; 228}; 229 230#ifdef notyet 231struct he_group { 232 u32 rpbl_size, rpbl_qsize; 233 struct he_rpb_entry *rbpl_ba; 234}; 235#endif 236 237#define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc) 238 239struct he_vcc_table 240{ 241 struct atm_vcc *vcc; 242}; 243 244struct he_cs_stper 245{ 246 long pcr; 247 int inuse; 248}; 249 250#define HE_NUM_CS_STPER 16 251 252struct he_dev { 253 unsigned int number; 254 unsigned int irq; 255 void __iomem *membase; 256 257 char prod_id[30]; 258 char mac_addr[6]; 259 int media; 260 261 unsigned int vcibits, vpibits; 262 unsigned int cells_per_row; 263 unsigned int bytes_per_row; 264 unsigned int cells_per_lbuf; 265 unsigned int r0_numrows, r0_startrow, r0_numbuffs; 266 unsigned int r1_numrows, r1_startrow, r1_numbuffs; 267 unsigned int tx_numrows, tx_startrow, tx_numbuffs; 268 unsigned int buffer_limit; 269 270 struct he_vcc_table *he_vcc_table; 271 272#ifdef notyet 273 struct he_group group[HE_NUM_GROUPS]; 274#endif 275 struct he_cs_stper cs_stper[HE_NUM_CS_STPER]; 276 unsigned total_bw; 277 278 dma_addr_t irq_phys; 279 struct he_irq *irq_base, *irq_head, *irq_tail; 280 volatile unsigned *irq_tailoffset; 281 int irq_peak; 282 283 struct tasklet_struct tasklet; 284 struct dma_pool *tpd_pool; 285 struct list_head outstanding_tpds; 286 287 dma_addr_t tpdrq_phys; 288 struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head; 289 290 spinlock_t global_lock; /* 8.1.5 pci transaction ordering 291 error problem */ 292 dma_addr_t rbrq_phys; 293 struct he_rbrq *rbrq_base, *rbrq_head; 294 int rbrq_peak; 295 296 struct he_buff **rbpl_virt; 297 unsigned long *rbpl_table; 298 unsigned long rbpl_hint; 299 struct dma_pool *rbpl_pool; 300 dma_addr_t rbpl_phys; 301 struct he_rbp *rbpl_base, *rbpl_tail; 302 struct list_head rbpl_outstanding; 303 int rbpl_peak; 304 305 dma_addr_t tbrq_phys; 306 struct he_tbrq *tbrq_base, *tbrq_head; 307 int tbrq_peak; 308 309 dma_addr_t hsp_phys; 310 struct he_hsp *hsp; 311 312 struct pci_dev *pci_dev; 313 struct atm_dev *atm_dev; 314 struct he_dev *next; 315}; 316 317#define HE_MAXIOV 20 318 319struct he_vcc 320{ 321 struct list_head buffers; 322 int pdu_len; 323 int rc_index; 324 325 wait_queue_head_t rx_waitq; 326 wait_queue_head_t tx_waitq; 327}; 328 329#define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data)) 330 331#define PCI_VENDOR_ID_FORE 0x1127 332#define PCI_DEVICE_ID_FORE_HE 0x400 333 334#define GEN_CNTL_0 0x40 335#define INT_PROC_ENBL (1<<25) 336#define SLAVE_ENDIAN_MODE (1<<16) 337#define MRL_ENB (1<<5) 338#define MRM_ENB (1<<4) 339#define INIT_ENB (1<<2) 340#define IGNORE_TIMEOUT (1<<1) 341#define ENBL_64 (1<<0) 342 343#define MIN_PCI_LATENCY 32 /* errata 8.1.3 */ 344 345#define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data) 346 347#define he_is622(dev) ((dev)->media & 0x1) 348#define he_isMM(dev) ((dev)->media & 0x20) 349 350#define HE_REGMAP_SIZE 0x100000 351 352#define RESET_CNTL 0x80000 353#define BOARD_RST_STATUS (1<<6) 354 355#define HOST_CNTL 0x80004 356#define PCI_BUS_SIZE64 (1<<27) 357#define DESC_RD_STATIC_64 (1<<26) 358#define DATA_RD_STATIC_64 (1<<25) 359#define DATA_WR_STATIC_64 (1<<24) 360#define ID_CS (1<<12) 361#define ID_WREN (1<<11) 362#define ID_DOUT (1<<10) 363#define ID_DOFFSET 10 364#define ID_DIN (1<<9) 365#define ID_CLOCK (1<<8) 366#define QUICK_RD_RETRY (1<<7) 367#define QUICK_WR_RETRY (1<<6) 368#define OUTFF_ENB (1<<5) 369#define CMDFF_ENB (1<<4) 370#define PERR_INT_ENB (1<<2) 371#define IGNORE_INTR (1<<0) 372 373#define LB_SWAP 0x80008 374#define SWAP_RNUM_MAX(x) (x<<27) 375#define DATA_WR_SWAP (1<<20) 376#define DESC_RD_SWAP (1<<19) 377#define DATA_RD_SWAP (1<<18) 378#define INTR_SWAP (1<<17) 379#define DESC_WR_SWAP (1<<16) 380#define SDRAM_INIT (1<<15) 381#define BIG_ENDIAN_HOST (1<<14) 382#define XFER_SIZE (1<<7) 383 384#define LB_MEM_ADDR 0x8000c 385#define LB_MEM_DATA 0x80010 386 387#define LB_MEM_ACCESS 0x80014 388#define LB_MEM_HNDSHK (1<<30) 389#define LM_MEM_WRITE (0x7) 390#define LM_MEM_READ (0x3) 391 392#define SDRAM_CTL 0x80018 393#define LB_64_ENB (1<<3) 394#define LB_TWR (1<<2) 395#define LB_TRP (1<<1) 396#define LB_TRAS (1<<0) 397 398#define INT_FIFO 0x8001c 399#define INT_MASK_D (1<<15) 400#define INT_MASK_C (1<<14) 401#define INT_MASK_B (1<<13) 402#define INT_MASK_A (1<<12) 403#define INT_CLEAR_D (1<<11) 404#define INT_CLEAR_C (1<<10) 405#define INT_CLEAR_B (1<<9) 406#define INT_CLEAR_A (1<<8) 407 408#define ABORT_ADDR 0x80020 409 410#define IRQ0_BASE 0x80080 411#define IRQ_BASE(x) (x<<12) 412#define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */ 413#define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK) 414#define IRQ0_HEAD 0x80084 415#define IRQ_SIZE(x) (x<<22) 416#define IRQ_THRESH(x) (x<<12) 417#define IRQ_HEAD(x) (x<<2) 418/* #define IRQ_PENDING (1) conflict with linux/irq.h */ 419#define IRQ0_CNTL 0x80088 420#define IRQ_ADDRSEL(x) (x<<2) 421#define IRQ_INT_A (0<<2) 422#define IRQ_INT_B (1<<2) 423#define IRQ_INT_C (2<<2) 424#define IRQ_INT_D (3<<2) 425#define IRQ_TYPE_ADDR 0x1 426#define IRQ_TYPE_LINE 0x0 427#define IRQ0_DATA 0x8008c 428 429#define IRQ1_BASE 0x80090 430#define IRQ1_HEAD 0x80094 431#define IRQ1_CNTL 0x80098 432#define IRQ1_DATA 0x8009c 433 434#define IRQ2_BASE 0x800a0 435#define IRQ2_HEAD 0x800a4 436#define IRQ2_CNTL 0x800a8 437#define IRQ2_DATA 0x800ac 438 439#define IRQ3_BASE 0x800b0 440#define IRQ3_HEAD 0x800b4 441#define IRQ3_CNTL 0x800b8 442#define IRQ3_DATA 0x800bc 443 444#define GRP_10_MAP 0x800c0 445#define GRP_32_MAP 0x800c4 446#define GRP_54_MAP 0x800c8 447#define GRP_76_MAP 0x800cc 448 449#define G0_RBPS_S 0x80400 450#define G0_RBPS_T 0x80404 451#define RBP_TAIL(x) ((x)<<3) 452#define RBP_MASK(x) ((x)|0x1fff) 453#define G0_RBPS_QI 0x80408 454#define RBP_QSIZE(x) ((x)<<14) 455#define RBP_INT_ENB (1<<13) 456#define RBP_THRESH(x) (x) 457#define G0_RBPS_BS 0x8040c 458#define G0_RBPL_S 0x80410 459#define G0_RBPL_T 0x80414 460#define G0_RBPL_QI 0x80418 461#define G0_RBPL_BS 0x8041c 462 463#define G1_RBPS_S 0x80420 464#define G1_RBPS_T 0x80424 465#define G1_RBPS_QI 0x80428 466#define G1_RBPS_BS 0x8042c 467#define G1_RBPL_S 0x80430 468#define G1_RBPL_T 0x80434 469#define G1_RBPL_QI 0x80438 470#define G1_RBPL_BS 0x8043c 471 472#define G2_RBPS_S 0x80440 473#define G2_RBPS_T 0x80444 474#define G2_RBPS_QI 0x80448 475#define G2_RBPS_BS 0x8044c 476#define G2_RBPL_S 0x80450 477#define G2_RBPL_T 0x80454 478#define G2_RBPL_QI 0x80458 479#define G2_RBPL_BS 0x8045c 480 481#define G3_RBPS_S 0x80460 482#define G3_RBPS_T 0x80464 483#define G3_RBPS_QI 0x80468 484#define G3_RBPS_BS 0x8046c 485#define G3_RBPL_S 0x80470 486#define G3_RBPL_T 0x80474 487#define G3_RBPL_QI 0x80478 488#define G3_RBPL_BS 0x8047c 489 490#define G4_RBPS_S 0x80480 491#define G4_RBPS_T 0x80484 492#define G4_RBPS_QI 0x80488 493#define G4_RBPS_BS 0x8048c 494#define G4_RBPL_S 0x80490 495#define G4_RBPL_T 0x80494 496#define G4_RBPL_QI 0x80498 497#define G4_RBPL_BS 0x8049c 498 499#define G5_RBPS_S 0x804a0 500#define G5_RBPS_T 0x804a4 501#define G5_RBPS_QI 0x804a8 502#define G5_RBPS_BS 0x804ac 503#define G5_RBPL_S 0x804b0 504#define G5_RBPL_T 0x804b4 505#define G5_RBPL_QI 0x804b8 506#define G5_RBPL_BS 0x804bc 507 508#define G6_RBPS_S 0x804c0 509#define G6_RBPS_T 0x804c4 510#define G6_RBPS_QI 0x804c8 511#define G6_RBPS_BS 0x804cc 512#define G6_RBPL_S 0x804d0 513#define G6_RBPL_T 0x804d4 514#define G6_RBPL_QI 0x804d8 515#define G6_RBPL_BS 0x804dc 516 517#define G7_RBPS_S 0x804e0 518#define G7_RBPS_T 0x804e4 519#define G7_RBPS_QI 0x804e8 520#define G7_RBPS_BS 0x804ec 521 522#define G7_RBPL_S 0x804f0 523#define G7_RBPL_T 0x804f4 524#define G7_RBPL_QI 0x804f8 525#define G7_RBPL_BS 0x804fc 526 527#define G0_RBRQ_ST 0x80500 528#define G0_RBRQ_H 0x80504 529#define G0_RBRQ_Q 0x80508 530#define RBRQ_THRESH(x) ((x)<<13) 531#define RBRQ_SIZE(x) (x) 532#define G0_RBRQ_I 0x8050c 533#define RBRQ_TIME(x) ((x)<<8) 534#define RBRQ_COUNT(x) (x) 535 536/* fill in 1 ... 7 later */ 537 538#define G0_TBRQ_B_T 0x80600 539#define G0_TBRQ_H 0x80604 540#define G0_TBRQ_S 0x80608 541#define G0_TBRQ_THRESH 0x8060c 542#define TBRQ_THRESH(x) (x) 543 544/* fill in 1 ... 7 later */ 545 546#define RH_CONFIG 0x805c0 547#define PHY_INT_ENB (1<<10) 548#define OAM_GID(x) (x<<7) 549#define PTMR_PRE(x) (x) 550 551#define G0_INMQ_S 0x80580 552#define G0_INMQ_L 0x80584 553#define G1_INMQ_S 0x80588 554#define G1_INMQ_L 0x8058c 555#define G2_INMQ_S 0x80590 556#define G2_INMQ_L 0x80594 557#define G3_INMQ_S 0x80598 558#define G3_INMQ_L 0x8059c 559#define G4_INMQ_S 0x805a0 560#define G4_INMQ_L 0x805a4 561#define G5_INMQ_S 0x805a8 562#define G5_INMQ_L 0x805ac 563#define G6_INMQ_S 0x805b0 564#define G6_INMQ_L 0x805b4 565#define G7_INMQ_S 0x805b8 566#define G7_INMQ_L 0x805bc 567 568#define TPDRQ_B_H 0x80680 569#define TPDRQ_T 0x80684 570#define TPDRQ_S 0x80688 571 572#define UBUFF_BA 0x8068c 573 574#define RLBF0_H 0x806c0 575#define RLBF0_T 0x806c4 576#define RLBF1_H 0x806c8 577#define RLBF1_T 0x806cc 578#define RLBC_H 0x806d0 579#define RLBC_T 0x806d4 580#define RLBC_H2 0x806d8 581#define TLBF_H 0x806e0 582#define TLBF_T 0x806e4 583#define RLBF0_C 0x806e8 584#define RLBF1_C 0x806ec 585#define RXTHRSH 0x806f0 586#define LITHRSH 0x806f4 587 588#define LBARB 0x80700 589#define SLICE_X(x) (x<<28) 590#define ARB_RNUM_MAX(x) (x<<23) 591#define TH_PRTY(x) (x<<21) 592#define RH_PRTY(x) (x<<19) 593#define TL_PRTY(x) (x<<17) 594#define RL_PRTY(x) (x<<15) 595#define BUS_MULTI(x) (x<<8) 596#define NET_PREF(x) (x) 597 598#define SDRAMCON 0x80704 599#define BANK_ON (1<<14) 600#define WIDE_DATA (1<<13) 601#define TWR_WAIT (1<<12) 602#define TRP_WAIT (1<<11) 603#define TRAS_WAIT (1<<10) 604#define REF_RATE(x) (x) 605 606#define LBSTAT 0x80708 607 608#define RCC_STAT 0x8070c 609#define RCC_BUSY (1) 610 611#define TCMCONFIG 0x80740 612#define TM_DESL2 (1<<10) 613#define TM_BANK_WAIT(x) (x<<6) 614#define TM_ADD_BANK4(x) (x<<4) 615#define TM_PAR_CHECK(x) (x<<3) 616#define TM_RW_WAIT(x) (x<<2) 617#define TM_SRAM_TYPE(x) (x) 618 619#define TSRB_BA 0x80744 620#define TSRC_BA 0x80748 621#define TMABR_BA 0x8074c 622#define TPD_BA 0x80750 623#define TSRD_BA 0x80758 624 625#define TX_CONFIG 0x80760 626#define DRF_THRESH(x) (x<<22) 627#define TX_UT_MODE(x) (x<<21) 628#define TX_VCI_MASK(x) (x<<17) 629#define LBFREE_CNT(x) (x) 630 631#define TXAAL5_PROTO 0x80764 632#define CPCS_UU(x) (x<<8) 633#define CPI(x) (x) 634 635#define RCMCONFIG 0x80780 636#define RM_DESL2(x) (x<<10) 637#define RM_BANK_WAIT(x) (x<<6) 638#define RM_ADD_BANK(x) (x<<4) 639#define RM_PAR_CHECK(x) (x<<3) 640#define RM_RW_WAIT(x) (x<<2) 641#define RM_SRAM_TYPE(x) (x) 642 643#define RCMRSRB_BA 0x80784 644#define RCMLBM_BA 0x80788 645#define RCMABR_BA 0x8078c 646 647#define RC_CONFIG 0x807c0 648#define UT_RD_DELAY(x) (x<<11) 649#define WRAP_MODE(x) (x<<10) 650#define RC_UT_MODE(x) (x<<9) 651#define RX_ENABLE (1<<8) 652#define RX_VALVP(x) (x<<4) 653#define RX_VALVC(x) (x) 654 655#define MCC 0x807c4 656#define OEC 0x807c8 657#define DCC 0x807cc 658#define CEC 0x807d0 659 660#define HSP_BA 0x807f0 661 662#define LB_CONFIG 0x807f4 663#define LB_SIZE(x) (x) 664 665#define CON_DAT 0x807f8 666#define CON_CTL 0x807fc 667#define CON_CTL_MBOX (2<<30) 668#define CON_CTL_TCM (1<<30) 669#define CON_CTL_RCM (0<<30) 670#define CON_CTL_WRITE (1<<29) 671#define CON_CTL_READ (0<<29) 672#define CON_CTL_BUSY (1<<28) 673#define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */ 674#define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */ 675#define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */ 676#define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */ 677#define CON_CTL_ADDR(x) (x) 678 679#define FRAMER 0x80800 /* to 0x80bfc */ 680 681/* 3.3 network controller (internal) mailbox registers */ 682 683#define CS_STPER0 0x0 684 /* ... */ 685#define CS_STPER31 0x01f 686 687#define CS_STTIM0 0x020 688 /* ... */ 689#define CS_STTIM31 0x03f 690 691#define CS_TGRLD0 0x040 692 /* ... */ 693#define CS_TGRLD15 0x04f 694 695#define CS_ERTHR0 0x050 696#define CS_ERTHR1 0x051 697#define CS_ERTHR2 0x052 698#define CS_ERTHR3 0x053 699#define CS_ERTHR4 0x054 700#define CS_ERCTL0 0x055 701#define TX_ENABLE (1<<28) 702#define ER_ENABLE (1<<27) 703#define CS_ERCTL1 0x056 704#define CS_ERCTL2 0x057 705#define CS_ERSTAT0 0x058 706#define CS_ERSTAT1 0x059 707 708#define CS_RTCCT 0x060 709#define CS_RTFWC 0x061 710#define CS_RTFWR 0x062 711#define CS_RTFTC 0x063 712#define CS_RTATR 0x064 713 714#define CS_TFBSET 0x070 715#define CS_TFBADD 0x071 716#define CS_TFBSUB 0x072 717#define CS_WCRMAX 0x073 718#define CS_WCRMIN 0x074 719#define CS_WCRINC 0x075 720#define CS_WCRDEC 0x076 721#define CS_WCRCEIL 0x077 722#define CS_BWDCNT 0x078 723 724#define CS_OTPPER 0x080 725#define CS_OTWPER 0x081 726#define CS_OTTLIM 0x082 727#define CS_OTTCNT 0x083 728 729#define CS_HGRRT0 0x090 730 /* ... */ 731#define CS_HGRRT7 0x097 732 733#define CS_ORPTRS 0x0a0 734 735#define RXCON_CLOSE 0x100 736 737 738#define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */ 739#define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */ 740 741/* 2.5 transmit connection memory registers */ 742 743#define TSR0_CONN_STATE(x) ((x>>28) & 0x7) 744#define TSR0_USE_WMIN (1<<23) 745#define TSR0_GROUP(x) ((x & 0x7)<<18) 746#define TSR0_ABR (2<<16) 747#define TSR0_UBR (1<<16) 748#define TSR0_CBR (0<<16) 749#define TSR0_PROT (1<<15) 750#define TSR0_AAL0_SDU (2<<12) 751#define TSR0_AAL0 (1<<12) 752#define TSR0_AAL5 (0<<12) 753#define TSR0_HALT_ER (1<<11) 754#define TSR0_MARK_CI (1<<10) 755#define TSR0_MARK_ER (1<<9) 756#define TSR0_UPDATE_GER (1<<8) 757#define TSR0_RC_INDEX(x) (x & 0x1F) 758 759#define TSR1_PCR(x) ((x & 0x7FFF)<<16) 760#define TSR1_MCR(x) (x & 0x7FFF) 761 762#define TSR2_ACR(x) ((x & 0x7FFF)<<16) 763 764#define TSR3_NRM_CNT(x) ((x & 0xFF)<<24) 765#define TSR3_CRM_CNT(x) (x & 0xFFFF) 766 767#define TSR4_FLUSH_CONN (1<<31) 768#define TSR4_SESSION_ENDED (1<<30) 769#define TSR4_CRC10 (1<<28) 770#define TSR4_NULL_CRC10 (1<<27) 771#define TSR4_PROT (1<<26) 772#define TSR4_AAL0_SDU (2<<23) 773#define TSR4_AAL0 (1<<23) 774#define TSR4_AAL5 (0<<23) 775 776#define TSR9_OPEN_CONN (1<<20) 777 778#define TSR11_ICR(x) ((x & 0x7FFF)<<16) 779#define TSR11_TRM(x) ((x & 0x7)<<13) 780#define TSR11_NRM(x) ((x & 0x7)<<10) 781#define TSR11_ADTF(x) (x & 0x3FF) 782 783#define TSR13_RDF(x) ((x & 0xF)<<23) 784#define TSR13_RIF(x) ((x & 0xF)<<19) 785#define TSR13_CDF(x) ((x & 0x7)<<16) 786#define TSR13_CRM(x) (x & 0xFFFF) 787 788#define TSR14_DELETE (1<<31) 789#define TSR14_ABR_CLOSE (1<<16) 790 791/* 2.7.1 per connection receieve state registers */ 792 793#define RSR0_START_PDU (1<<10) 794#define RSR0_OPEN_CONN (1<<6) 795#define RSR0_CLOSE_CONN (0<<6) 796#define RSR0_PPD_ENABLE (1<<5) 797#define RSR0_EPD_ENABLE (1<<4) 798#define RSR0_TCP_CKSUM (1<<3) 799#define RSR0_AAL5 (0) 800#define RSR0_AAL0 (1) 801#define RSR0_AAL0_SDU (2) 802#define RSR0_RAWCELL (3) 803#define RSR0_RAWCELL_CRC10 (4) 804 805#define RSR1_AQI_ENABLE (1<<20) 806#define RSR1_RBPL_ONLY (1<<19) 807#define RSR1_GROUP(x) ((x)<<16) 808 809#define RSR4_AQI_ENABLE (1<<30) 810#define RSR4_GROUP(x) ((x)<<27) 811#define RSR4_RBPL_ONLY (1<<26) 812 813/* 2.1.4 transmit packet descriptor */ 814 815#define TPD_USERCELL 0x0 816#define TPD_SEGMENT_OAMF5 0x4 817#define TPD_END2END_OAMF5 0x5 818#define TPD_RMCELL 0x6 819#define TPD_CELLTYPE(x) (x<<3) 820#define TPD_EOS (1<<2) 821#define TPD_CLP (1<<1) 822#define TPD_INT (1<<0) 823#define TPD_LST (1<<31) 824 825/* table 4.3 serial eeprom information */ 826 827#define PROD_ID 0x08 /* char[] */ 828#define PROD_ID_LEN 30 829#define HW_REV 0x26 /* char[] */ 830#define M_SN 0x3a /* integer */ 831#define MEDIA 0x3e /* integer */ 832#define HE155MM 0x26 833#define HE622MM 0x27 834#define HE155SM 0x46 835#define HE622SM 0x47 836#define MAC_ADDR 0x42 /* char[] */ 837 838#define CS_LOW 0x0 839#define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */ 840#define CLK_LOW 0x0 841#define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */ 842#define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */ 843#define EEPROM_DELAY 400 /* microseconds */ 844 845#endif /* _HE_H_ */ 846