Searched refs:CSR_READ_4 (Results 1 - 25 of 84) sorted by relevance

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/freebsd-11-stable/sys/arm/amlogic/aml8726/
H A Daml8726_rtc.c126 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
136 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
144 if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) )
152 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
164 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
171 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
182 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
185 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
201 (CSR_READ_4(sc, AML_RTC_0_REG) & ~AML_RTC_SEN));
227 data |= (CSR_READ_4(s
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H A Daml8726_gpio.c88 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[reg], 0) macro
224 if ((CSR_READ_4(sc, AML_GPIO_OE_N_REG) & mask) == 0) {
249 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask));
253 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask));
282 ((CSR_READ_4(sc, AML_GPIO_OUT_REG) & ~mask) | (value << pin)));
299 *value = (CSR_READ_4(sc, AML_GPIO_IN_REG) & mask) ? 1 : 0;
325 CSR_READ_4(sc, AML_GPIO_OUT_REG) ^ mask);
H A Daml8726_timer.c131 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
139 return CSR_READ_4(sc, AML_TIMER_E_REG);
154 (CSR_READ_4(sc, AML_TIMER_MUX_REG) |
198 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) |
215 (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN));
258 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) &
267 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN));
H A Daml8726_rng.c68 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
76 rn[0] = CSR_READ_4(sc, AML_RNG_0_REG);
77 rn[1] = CSR_READ_4(sc, AML_RNG_1_REG);
H A Daml8726_pic.c112 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
228 value = CSR_READ_4(aml8726_pic_sc, AML_PIC_STAT_REG(irq));
253 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
272 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
H A Daml8726_i2c.c87 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
194 (CSR_READ_4(sc, AML_I2C_CTRL_REG) | AML_I2C_MANUAL_SDA_O |
210 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SCL_I);
218 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SDA_I);
228 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) &
242 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) &
H A Daml8726_usb_phy-m6.c101 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
228 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
257 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG);
294 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG);
303 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG);
313 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG);
378 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG);
H A Daml8726_usb_phy-m3.c104 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
244 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
329 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
338 value = CSR_READ_4(sc, AML_USB_PHY_MISC_A_REG);
347 value = CSR_READ_4(sc, AML_USB_PHY_MISC_B_REG);
387 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
H A Daml8726_wdt.c101 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
129 (CSR_READ_4(sc, AML_WDT_CTRL_REG) &
150 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
241 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
H A Daml8726_sdxc-m8.c153 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
232 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
256 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
279 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
297 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
360 ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG);
531 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
546 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
578 isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG);
579 sndr = CSR_READ_4(s
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H A Daml8726_ccm.c76 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
136 value = CSR_READ_4(sc, g->addr);
H A Daml8726_clkmsr.c106 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
135 while ((CSR_READ_4(sc, AML_CLKMSR_0_REG) & AML_CLKMSR_0_BUSY) != 0)
143 value = (((CSR_READ_4(sc, AML_CLKMSR_2_REG) & AML_CLKMSR_2_RESULT_MASK)
/freebsd-11-stable/sys/dev/dc/
H A Ddcphy.c75 CSR_READ_4(sc, reg) | x)
79 CSR_READ_4(sc, reg) & ~x)
208 mode = CSR_READ_4(dc_sc, DC_NETCFG);
263 reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
309 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
313 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
366 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
370 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
H A Dpnphy.c209 reg = CSR_READ_4(dc_sc, DC_ISR);
212 reg = CSR_READ_4(dc_sc, DC_NETCFG);
/freebsd-11-stable/sys/dev/et/
H A Dif_et.c438 val = CSR_READ_4(sc, ET_MII_IND);
452 val = CSR_READ_4(sc, ET_MII_STAT);
483 val = CSR_READ_4(sc, ET_MII_IND);
538 ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
540 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
543 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
587 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
660 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~(
1189 status = CSR_READ_4(sc, ET_INTR_STATUS);
1484 if ((CSR_READ_4(s
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/freebsd-11-stable/sys/dev/bge/
H A Dif_bge.c668 CSR_READ_4(sc, off);
1010 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1018 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1025 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1037 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1046 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1102 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1112 byte = CSR_READ_4(sc, BGE_EE_DATA);
1163 val = CSR_READ_4(sc, BGE_MI_COMM);
1166 val = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/bfe/
H A Dif_bfe.c671 val = CSR_READ_4(sc, BFE_TX_CTRL);
677 flow = CSR_READ_4(sc, BFE_RXCONF);
687 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
864 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
866 val = CSR_READ_4(sc, BFE_SBINTVEC);
870 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
886 CSR_READ_4(sc, reg);
888 CSR_READ_4(sc, reg);
912 CSR_READ_4(sc, BFE_IMASK);
933 val = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/alc/
H A Dif_alc.c298 v = CSR_READ_4(sc, ALC_MDIO);
325 v = CSR_READ_4(sc, ALC_MDIO);
363 v = CSR_READ_4(sc, ALC_MDIO);
389 v = CSR_READ_4(sc, ALC_MDIO);
440 reg = CSR_READ_4(sc, ALC_MAC_CFG);
484 v = CSR_READ_4(sc, ALC_MDIO);
515 v = CSR_READ_4(sc, ALC_MDIO);
698 opt = CSR_READ_4(sc, ALC_OPT_CFG);
699 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
700 (CSR_READ_4(s
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/freebsd-11-stable/sys/dev/vx/
H A Dif_vxvar.h67 #define CSR_READ_4(sc, reg) \ macro
/freebsd-11-stable/sys/dev/nge/
H A Dif_nge.c248 CSR_READ_4(sc, reg) | (x))
252 CSR_READ_4(sc, reg) & ~(x))
255 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
258 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
266 CSR_READ_4(sc, NGE_CSR);
350 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
390 val = CSR_READ_4(sc, NGE_MEAR);
430 reg = CSR_READ_4(sc, NGE_TBI_BMSR);
456 return (CSR_READ_4(sc, reg));
590 reg = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/sis/
H A Dif_sis.c120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) macro
196 CSR_READ_4(sc, reg) | (x))
200 CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
229 CSR_READ_4(sc, SIS_CSR);
313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
416 csrsave = CSR_READ_4(sc, SIS_CSR);
446 val = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/jme/
H A Dif_jme.c231 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
263 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
359 reg = CSR_READ_4(sc, JME_SMBCSR);
374 reg = CSR_READ_4(sc, JME_SMBINTF);
384 reg = CSR_READ_4(sc, JME_SMBINTF);
492 par0 = CSR_READ_4(sc, JME_PAR0);
493 par1 = CSR_READ_4(sc, JME_PAR1);
711 reg = CSR_READ_4(sc, JME_CHIPMODE);
754 reg = CSR_READ_4(sc, JME_SMBCSR);
770 sc->jme_phyaddr = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/bwi/
H A Dbwimac.c198 return CSR_READ_4(sc, BWI_MOBJ_DATA);
247 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */
462 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
468 CSR_READ_4(sc, BWI_STATE_LO);
474 CSR_READ_4(sc, BWI_STATE_LO);
479 status = CSR_READ_4(sc, BWI_MAC_STATUS);
569 val = CSR_READ_4(sc, BWI_MAC_STATUS);
576 val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
718 CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */
1054 intr_status = CSR_READ_4(s
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/freebsd-11-stable/sys/dev/vge/
H A Dif_vgevar.h224 #define CSR_READ_4(sc, reg) \ macro
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/freebsd-11-stable/sys/dev/lge/
H A Dif_lge.c198 CSR_READ_4(sc, reg) | (x))
202 CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
226 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
234 val = CSR_READ_4(sc, LGE_EEDATA);
291 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
299 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
316 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
421 if (!(CSR_READ_4(s
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