1139749Simp/*- 276479Swpaul * Copyright (c) 2001 Wind River Systems 376479Swpaul * Copyright (c) 1997, 1998, 1999, 2000, 2001 476479Swpaul * Bill Paul <wpaul@bsdi.com>. All rights reserved. 576479Swpaul * 676479Swpaul * Redistribution and use in source and binary forms, with or without 776479Swpaul * modification, are permitted provided that the following conditions 876479Swpaul * are met: 976479Swpaul * 1. Redistributions of source code must retain the above copyright 1076479Swpaul * notice, this list of conditions and the following disclaimer. 1176479Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1276479Swpaul * notice, this list of conditions and the following disclaimer in the 1376479Swpaul * documentation and/or other materials provided with the distribution. 1476479Swpaul * 3. All advertising materials mentioning features or use of this software 1576479Swpaul * must display the following acknowledgement: 1676479Swpaul * This product includes software developed by Bill Paul. 1776479Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1876479Swpaul * may be used to endorse or promote products derived from this software 1976479Swpaul * without specific prior written permission. 2076479Swpaul * 2176479Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2276479Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2376479Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2476479Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2576479Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2676479Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2776479Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2876479Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2976479Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3076479Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3176479Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3276479Swpaul */ 3376479Swpaul 34119418Sobrien#include <sys/cdefs.h> 35119418Sobrien__FBSDID("$FreeBSD$"); 36119418Sobrien 3776479Swpaul/* 3876479Swpaul * National Semiconductor DP83820/DP83821 gigabit ethernet driver 3976479Swpaul * for FreeBSD. Datasheets are available from: 4076479Swpaul * 4176479Swpaul * http://www.national.com/ds/DP/DP83820.pdf 4276479Swpaul * http://www.national.com/ds/DP/DP83821.pdf 4376479Swpaul * 4476479Swpaul * These chips are used on several low cost gigabit ethernet NICs 4576479Swpaul * sold by D-Link, Addtron, SMC and Asante. Both parts are 4676479Swpaul * virtually the same, except the 83820 is a 64-bit/32-bit part, 4776479Swpaul * while the 83821 is 32-bit only. 4876479Swpaul * 4976479Swpaul * Many cards also use National gigE transceivers, such as the 5076479Swpaul * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 5176479Swpaul * contains a full register description that applies to all of these 5276479Swpaul * components: 5376479Swpaul * 5476479Swpaul * http://www.national.com/ds/DP/DP83861.pdf 5576479Swpaul * 5676479Swpaul * Written by Bill Paul <wpaul@bsdi.com> 5776479Swpaul * BSDi Open Source Solutions 5876479Swpaul */ 5976479Swpaul 6076479Swpaul/* 6176479Swpaul * The NatSemi DP83820 and 83821 controllers are enhanced versions 6276479Swpaul * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 6376479Swpaul * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 6476479Swpaul * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 6576479Swpaul * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 6676479Swpaul * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 6776479Swpaul * matching buffers, one perfect address filter buffer and interrupt 6876479Swpaul * moderation. The 83820 supports both 64-bit and 32-bit addressing 6976479Swpaul * and data transfers: the 64-bit support can be toggled on or off 7076479Swpaul * via software. This affects the size of certain fields in the DMA 7176479Swpaul * descriptors. 7276479Swpaul * 7378323Swpaul * There are two bugs/misfeatures in the 83820/83821 that I have 7478323Swpaul * discovered so far: 7578323Swpaul * 7678323Swpaul * - Receive buffers must be aligned on 64-bit boundaries, which means 7778323Swpaul * you must resort to copying data in order to fix up the payload 7878323Swpaul * alignment. 7978323Swpaul * 8078323Swpaul * - In order to transmit jumbo frames larger than 8170 bytes, you have 8178323Swpaul * to turn off transmit checksum offloading, because the chip can't 8278323Swpaul * compute the checksum on an outgoing frame unless it fits entirely 8378323Swpaul * within the TX FIFO, which is only 8192 bytes in size. If you have 8478323Swpaul * TX checksum offload enabled and you transmit attempt to transmit a 8578323Swpaul * frame larger than 8170 bytes, the transmitter will wedge. 8678323Swpaul * 8778323Swpaul * To work around the latter problem, TX checksum offload is disabled 8878323Swpaul * if the user selects an MTU larger than 8152 (8170 - 18). 8976479Swpaul */ 9076479Swpaul 91150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 92150968Sglebius#include "opt_device_polling.h" 93150968Sglebius#endif 94150968Sglebius 9576479Swpaul#include <sys/param.h> 9676479Swpaul#include <sys/systm.h> 97192506Syongari#include <sys/bus.h> 98192506Syongari#include <sys/endian.h> 99192506Syongari#include <sys/kernel.h> 100192506Syongari#include <sys/lock.h> 101192506Syongari#include <sys/malloc.h> 10276479Swpaul#include <sys/mbuf.h> 103129879Sphk#include <sys/module.h> 104192506Syongari#include <sys/mutex.h> 105192506Syongari#include <sys/rman.h> 10676479Swpaul#include <sys/socket.h> 107192506Syongari#include <sys/sockio.h> 108192506Syongari#include <sys/sysctl.h> 10976479Swpaul 110192506Syongari#include <net/bpf.h> 11176479Swpaul#include <net/if.h> 112257176Sglebius#include <net/if_var.h> 11376479Swpaul#include <net/if_arp.h> 11476479Swpaul#include <net/ethernet.h> 11576479Swpaul#include <net/if_dl.h> 11676479Swpaul#include <net/if_media.h> 11776479Swpaul#include <net/if_types.h> 11876479Swpaul#include <net/if_vlan_var.h> 11976479Swpaul 12076479Swpaul#include <dev/mii/mii.h> 121226995Smarius#include <dev/mii/mii_bitbang.h> 12276479Swpaul#include <dev/mii/miivar.h> 12376479Swpaul 124119285Simp#include <dev/pci/pcireg.h> 125119285Simp#include <dev/pci/pcivar.h> 12676479Swpaul 127192506Syongari#include <machine/bus.h> 12876479Swpaul 12976522Swpaul#include <dev/nge/if_ngereg.h> 13076479Swpaul 131192506Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 132192506Syongari#include "miibus_if.h" 133192506Syongari 134113506SmdoddMODULE_DEPEND(nge, pci, 1, 1, 1); 135113506SmdoddMODULE_DEPEND(nge, ether, 1, 1, 1); 13676479SwpaulMODULE_DEPEND(nge, miibus, 1, 1, 1); 13776479Swpaul 13876479Swpaul#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 13976479Swpaul 14076479Swpaul/* 14176479Swpaul * Various supported device vendors/types and their names. 14276479Swpaul */ 143242625Sdimstatic const struct nge_type nge_devs[] = { 14476479Swpaul { NGE_VENDORID, NGE_DEVICEID, 14576479Swpaul "National Semiconductor Gigabit Ethernet" }, 14676479Swpaul { 0, 0, NULL } 14776479Swpaul}; 14876479Swpaul 14999497Salfredstatic int nge_probe(device_t); 15099497Salfredstatic int nge_attach(device_t); 15199497Salfredstatic int nge_detach(device_t); 152192506Syongaristatic int nge_shutdown(device_t); 153192506Syongaristatic int nge_suspend(device_t); 154192506Syongaristatic int nge_resume(device_t); 15576479Swpaul 156192506Syongaristatic __inline void nge_discard_rxbuf(struct nge_softc *, int); 157192506Syongaristatic int nge_newbuf(struct nge_softc *, int); 158192506Syongaristatic int nge_encap(struct nge_softc *, struct mbuf **); 159192506Syongari#ifndef __NO_STRICT_ALIGNMENT 160192506Syongaristatic __inline void nge_fixup_rx(struct mbuf *); 161135250Swpaul#endif 162193105Sattiliostatic int nge_rxeof(struct nge_softc *); 16399497Salfredstatic void nge_txeof(struct nge_softc *); 16499497Salfredstatic void nge_intr(void *); 16599497Salfredstatic void nge_tick(void *); 166192506Syongaristatic void nge_stats_update(struct nge_softc *); 16799497Salfredstatic void nge_start(struct ifnet *); 168135250Swpaulstatic void nge_start_locked(struct ifnet *); 16999497Salfredstatic int nge_ioctl(struct ifnet *, u_long, caddr_t); 17099497Salfredstatic void nge_init(void *); 171135250Swpaulstatic void nge_init_locked(struct nge_softc *); 172192506Syongaristatic int nge_stop_mac(struct nge_softc *); 17399497Salfredstatic void nge_stop(struct nge_softc *); 174192506Syongaristatic void nge_wol(struct nge_softc *); 175192506Syongaristatic void nge_watchdog(struct nge_softc *); 176192506Syongaristatic int nge_mediachange(struct ifnet *); 177192506Syongaristatic void nge_mediastatus(struct ifnet *, struct ifmediareq *); 17876479Swpaul 17999497Salfredstatic void nge_delay(struct nge_softc *); 18099497Salfredstatic void nge_eeprom_idle(struct nge_softc *); 18199497Salfredstatic void nge_eeprom_putbyte(struct nge_softc *, int); 182192294Syongaristatic void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 183192506Syongaristatic void nge_read_eeprom(struct nge_softc *, caddr_t, int, int); 18476479Swpaul 18599497Salfredstatic int nge_miibus_readreg(device_t, int, int); 18699497Salfredstatic int nge_miibus_writereg(device_t, int, int, int); 18799497Salfredstatic void nge_miibus_statchg(device_t); 18876479Swpaul 189192506Syongaristatic void nge_rxfilter(struct nge_softc *); 19099497Salfredstatic void nge_reset(struct nge_softc *); 191192506Syongaristatic void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 192192506Syongaristatic int nge_dma_alloc(struct nge_softc *); 193192506Syongaristatic void nge_dma_free(struct nge_softc *); 19499497Salfredstatic int nge_list_rx_init(struct nge_softc *); 19599497Salfredstatic int nge_list_tx_init(struct nge_softc *); 196192506Syongaristatic void nge_sysctl_node(struct nge_softc *); 197192506Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 198192506Syongaristatic int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS); 19976479Swpaul 200226995Smarius/* 201226995Smarius * MII bit-bang glue 202226995Smarius */ 203226995Smariusstatic uint32_t nge_mii_bitbang_read(device_t); 204226995Smariusstatic void nge_mii_bitbang_write(device_t, uint32_t); 205226995Smarius 206226995Smariusstatic const struct mii_bitbang_ops nge_mii_bitbang_ops = { 207226995Smarius nge_mii_bitbang_read, 208226995Smarius nge_mii_bitbang_write, 209226995Smarius { 210226995Smarius NGE_MEAR_MII_DATA, /* MII_BIT_MDO */ 211226995Smarius NGE_MEAR_MII_DATA, /* MII_BIT_MDI */ 212226995Smarius NGE_MEAR_MII_CLK, /* MII_BIT_MDC */ 213226995Smarius NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 214226995Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 215226995Smarius } 216226995Smarius}; 217226995Smarius 21876479Swpaulstatic device_method_t nge_methods[] = { 21976479Swpaul /* Device interface */ 22076479Swpaul DEVMETHOD(device_probe, nge_probe), 22176479Swpaul DEVMETHOD(device_attach, nge_attach), 22276479Swpaul DEVMETHOD(device_detach, nge_detach), 22376479Swpaul DEVMETHOD(device_shutdown, nge_shutdown), 224192506Syongari DEVMETHOD(device_suspend, nge_suspend), 225192506Syongari DEVMETHOD(device_resume, nge_resume), 22676479Swpaul 22776479Swpaul /* MII interface */ 22876479Swpaul DEVMETHOD(miibus_readreg, nge_miibus_readreg), 22976479Swpaul DEVMETHOD(miibus_writereg, nge_miibus_writereg), 23076479Swpaul DEVMETHOD(miibus_statchg, nge_miibus_statchg), 23176479Swpaul 232227843Smarius DEVMETHOD_END 23376479Swpaul}; 23476479Swpaul 23576479Swpaulstatic driver_t nge_driver = { 23676479Swpaul "nge", 23776479Swpaul nge_methods, 23876479Swpaul sizeof(struct nge_softc) 23976479Swpaul}; 24076479Swpaul 24176479Swpaulstatic devclass_t nge_devclass; 24276479Swpaul 243113506SmdoddDRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 24476479SwpaulDRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 24576479Swpaul 24676479Swpaul#define NGE_SETBIT(sc, reg, x) \ 24776479Swpaul CSR_WRITE_4(sc, reg, \ 24876479Swpaul CSR_READ_4(sc, reg) | (x)) 24976479Swpaul 25076479Swpaul#define NGE_CLRBIT(sc, reg, x) \ 25176479Swpaul CSR_WRITE_4(sc, reg, \ 25276479Swpaul CSR_READ_4(sc, reg) & ~(x)) 25376479Swpaul 25476479Swpaul#define SIO_SET(x) \ 255106696Salfred CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 25676479Swpaul 25776479Swpaul#define SIO_CLR(x) \ 258106696Salfred CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 25976479Swpaul 26099497Salfredstatic void 261192288Syongaringe_delay(struct nge_softc *sc) 26276479Swpaul{ 263192297Syongari int idx; 26476479Swpaul 26576479Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 26676479Swpaul CSR_READ_4(sc, NGE_CSR); 26776479Swpaul} 26876479Swpaul 26999497Salfredstatic void 270192288Syongaringe_eeprom_idle(struct nge_softc *sc) 27176479Swpaul{ 272192297Syongari int i; 27376479Swpaul 27476479Swpaul SIO_SET(NGE_MEAR_EE_CSEL); 27576479Swpaul nge_delay(sc); 27676479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 27776479Swpaul nge_delay(sc); 27876479Swpaul 27976479Swpaul for (i = 0; i < 25; i++) { 28076479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 28176479Swpaul nge_delay(sc); 28276479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 28376479Swpaul nge_delay(sc); 28476479Swpaul } 28576479Swpaul 28676479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 28776479Swpaul nge_delay(sc); 28876479Swpaul SIO_CLR(NGE_MEAR_EE_CSEL); 28976479Swpaul nge_delay(sc); 29076479Swpaul CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 29176479Swpaul} 29276479Swpaul 29376479Swpaul/* 29476479Swpaul * Send a read command and address to the EEPROM, check for ACK. 29576479Swpaul */ 29699497Salfredstatic void 297192288Syongaringe_eeprom_putbyte(struct nge_softc *sc, int addr) 29876479Swpaul{ 299192297Syongari int d, i; 30076479Swpaul 30176479Swpaul d = addr | NGE_EECMD_READ; 30276479Swpaul 30376479Swpaul /* 30476479Swpaul * Feed in each bit and stobe the clock. 30576479Swpaul */ 30676479Swpaul for (i = 0x400; i; i >>= 1) { 30776479Swpaul if (d & i) { 30876479Swpaul SIO_SET(NGE_MEAR_EE_DIN); 30976479Swpaul } else { 31076479Swpaul SIO_CLR(NGE_MEAR_EE_DIN); 31176479Swpaul } 31276479Swpaul nge_delay(sc); 31376479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 31476479Swpaul nge_delay(sc); 31576479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 31676479Swpaul nge_delay(sc); 31776479Swpaul } 31876479Swpaul} 31976479Swpaul 32076479Swpaul/* 32176479Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 32276479Swpaul */ 32399497Salfredstatic void 324192294Syongaringe_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 32576479Swpaul{ 326192297Syongari int i; 327192297Syongari uint16_t word = 0; 32876479Swpaul 32976479Swpaul /* Force EEPROM to idle state. */ 33076479Swpaul nge_eeprom_idle(sc); 33176479Swpaul 33276479Swpaul /* Enter EEPROM access mode. */ 33376479Swpaul nge_delay(sc); 33476479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 33576479Swpaul nge_delay(sc); 33676479Swpaul SIO_SET(NGE_MEAR_EE_CSEL); 33776479Swpaul nge_delay(sc); 33876479Swpaul 33976479Swpaul /* 34076479Swpaul * Send address of word we want to read. 34176479Swpaul */ 34276479Swpaul nge_eeprom_putbyte(sc, addr); 34376479Swpaul 34476479Swpaul /* 34576479Swpaul * Start reading bits from EEPROM. 34676479Swpaul */ 34776479Swpaul for (i = 0x8000; i; i >>= 1) { 34876479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 34976479Swpaul nge_delay(sc); 35076479Swpaul if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 35176479Swpaul word |= i; 35276479Swpaul nge_delay(sc); 35376479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 35476479Swpaul nge_delay(sc); 35576479Swpaul } 35676479Swpaul 35776479Swpaul /* Turn off EEPROM access mode. */ 35876479Swpaul nge_eeprom_idle(sc); 35976479Swpaul 36076479Swpaul *dest = word; 36176479Swpaul} 36276479Swpaul 36376479Swpaul/* 36476479Swpaul * Read a sequence of words from the EEPROM. 36576479Swpaul */ 36699497Salfredstatic void 367192506Syongaringe_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt) 36876479Swpaul{ 369192297Syongari int i; 370192297Syongari uint16_t word = 0, *ptr; 37176479Swpaul 37276479Swpaul for (i = 0; i < cnt; i++) { 37376479Swpaul nge_eeprom_getword(sc, off + i, &word); 374192294Syongari ptr = (uint16_t *)(dest + (i * 2)); 375192506Syongari *ptr = word; 37676479Swpaul } 37776479Swpaul} 37876479Swpaul 37976479Swpaul/* 380226995Smarius * Read the MII serial port for the MII bit-bang module. 38176479Swpaul */ 382226995Smariusstatic uint32_t 383226995Smariusnge_mii_bitbang_read(device_t dev) 38476479Swpaul{ 385226995Smarius struct nge_softc *sc; 386226995Smarius uint32_t val; 38776479Swpaul 388226995Smarius sc = device_get_softc(dev); 38976479Swpaul 390226995Smarius val = CSR_READ_4(sc, NGE_MEAR); 391226995Smarius CSR_BARRIER_4(sc, NGE_MEAR, 392226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 393226995Smarius 394226995Smarius return (val); 39576479Swpaul} 39676479Swpaul 39776479Swpaul/* 398226995Smarius * Write the MII serial port for the MII bit-bang module. 39976479Swpaul */ 40099497Salfredstatic void 401226995Smariusnge_mii_bitbang_write(device_t dev, uint32_t val) 40276479Swpaul{ 403226995Smarius struct nge_softc *sc; 40476479Swpaul 405226995Smarius sc = device_get_softc(dev); 40676479Swpaul 407226995Smarius CSR_WRITE_4(sc, NGE_MEAR, val); 408226995Smarius CSR_BARRIER_4(sc, NGE_MEAR, 409226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 41076479Swpaul} 41176479Swpaul 41299497Salfredstatic int 413192288Syongaringe_miibus_readreg(device_t dev, int phy, int reg) 41476479Swpaul{ 415192297Syongari struct nge_softc *sc; 416192506Syongari int rv; 41776479Swpaul 41876479Swpaul sc = device_get_softc(dev); 419192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 420192506Syongari /* Pretend PHY is at address 0. */ 421192506Syongari if (phy != 0) 422192506Syongari return (0); 423192506Syongari switch (reg) { 424192506Syongari case MII_BMCR: 425192506Syongari reg = NGE_TBI_BMCR; 426192506Syongari break; 427192506Syongari case MII_BMSR: 428192506Syongari /* 83820/83821 has different bit layout for BMSR. */ 429192506Syongari rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT; 430192506Syongari reg = CSR_READ_4(sc, NGE_TBI_BMSR); 431192506Syongari if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0) 432192506Syongari rv |= BMSR_ACOMP; 433192506Syongari if ((reg & NGE_TBIBMSR_LINKSTAT) != 0) 434192506Syongari rv |= BMSR_LINK; 435192506Syongari return (rv); 436192506Syongari case MII_ANAR: 437192506Syongari reg = NGE_TBI_ANAR; 438192506Syongari break; 439192506Syongari case MII_ANLPAR: 440192506Syongari reg = NGE_TBI_ANLPAR; 441192506Syongari break; 442192506Syongari case MII_ANER: 443192506Syongari reg = NGE_TBI_ANER; 444192506Syongari break; 445192506Syongari case MII_EXTSR: 446192506Syongari reg = NGE_TBI_ESR; 447192506Syongari break; 448192506Syongari case MII_PHYIDR1: 449192506Syongari case MII_PHYIDR2: 450192506Syongari return (0); 451192506Syongari default: 452192506Syongari device_printf(sc->nge_dev, 453192506Syongari "bad phy register read : %d\n", reg); 454192506Syongari return (0); 455192506Syongari } 456192506Syongari return (CSR_READ_4(sc, reg)); 457192506Syongari } 45876479Swpaul 459226995Smarius return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg)); 46076479Swpaul} 46176479Swpaul 46299497Salfredstatic int 463192288Syongaringe_miibus_writereg(device_t dev, int phy, int reg, int data) 46476479Swpaul{ 465192297Syongari struct nge_softc *sc; 46676479Swpaul 46776479Swpaul sc = device_get_softc(dev); 468192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 469192506Syongari /* Pretend PHY is at address 0. */ 470192506Syongari if (phy != 0) 471192506Syongari return (0); 472192506Syongari switch (reg) { 473192506Syongari case MII_BMCR: 474192506Syongari reg = NGE_TBI_BMCR; 475192506Syongari break; 476192506Syongari case MII_BMSR: 477192506Syongari return (0); 478192506Syongari case MII_ANAR: 479192506Syongari reg = NGE_TBI_ANAR; 480192506Syongari break; 481192506Syongari case MII_ANLPAR: 482192506Syongari reg = NGE_TBI_ANLPAR; 483192506Syongari break; 484192506Syongari case MII_ANER: 485192506Syongari reg = NGE_TBI_ANER; 486192506Syongari break; 487192506Syongari case MII_EXTSR: 488192506Syongari reg = NGE_TBI_ESR; 489192506Syongari break; 490192506Syongari case MII_PHYIDR1: 491192506Syongari case MII_PHYIDR2: 492192506Syongari return (0); 493192506Syongari default: 494192506Syongari device_printf(sc->nge_dev, 495192506Syongari "bad phy register write : %d\n", reg); 496192506Syongari return (0); 497192506Syongari } 498192506Syongari CSR_WRITE_4(sc, reg, data); 499192506Syongari return (0); 500192506Syongari } 50176479Swpaul 502226995Smarius mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data); 50376479Swpaul 504192292Syongari return (0); 50576479Swpaul} 50676479Swpaul 507192506Syongari/* 508192506Syongari * media status/link state change handler. 509192506Syongari */ 51099497Salfredstatic void 511192288Syongaringe_miibus_statchg(device_t dev) 51276479Swpaul{ 513192297Syongari struct nge_softc *sc; 514192297Syongari struct mii_data *mii; 515192506Syongari struct ifnet *ifp; 516192506Syongari struct nge_txdesc *txd; 517192506Syongari uint32_t done, reg, status; 518192506Syongari int i; 51976479Swpaul 52076479Swpaul sc = device_get_softc(dev); 521192506Syongari NGE_LOCK_ASSERT(sc); 52276479Swpaul 523192506Syongari mii = device_get_softc(sc->nge_miibus); 524192506Syongari ifp = sc->nge_ifp; 525192506Syongari if (mii == NULL || ifp == NULL || 526192506Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 527192506Syongari return; 528192506Syongari 529192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 530192506Syongari if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 531192506Syongari (IFM_AVALID | IFM_ACTIVE)) { 532192506Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 533192506Syongari case IFM_10_T: 534192506Syongari case IFM_100_TX: 535192506Syongari case IFM_1000_T: 536192506Syongari case IFM_1000_SX: 537192506Syongari case IFM_1000_LX: 538192506Syongari case IFM_1000_CX: 539192506Syongari sc->nge_flags |= NGE_FLAG_LINK; 540192506Syongari break; 541192506Syongari default: 542192506Syongari break; 543101540Sambrisko } 544192506Syongari } 54576479Swpaul 546192506Syongari /* Stop Tx/Rx MACs. */ 547192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 548192506Syongari device_printf(sc->nge_dev, 549192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 550192506Syongari nge_txeof(sc); 551192506Syongari nge_rxeof(sc); 552192506Syongari if (sc->nge_head != NULL) { 553192506Syongari m_freem(sc->nge_head); 554192506Syongari sc->nge_head = sc->nge_tail = NULL; 555192506Syongari } 556192506Syongari 557192506Syongari /* Release queued frames. */ 558192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 559192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 560192506Syongari if (txd->tx_m != NULL) { 561192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 562192506Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 563192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 564192506Syongari txd->tx_dmamap); 565192506Syongari m_freem(txd->tx_m); 566192506Syongari txd->tx_m = NULL; 567192506Syongari } 568192506Syongari } 569192506Syongari 570192506Syongari /* Program MAC with resolved speed/duplex. */ 571192506Syongari if ((sc->nge_flags & NGE_FLAG_LINK) != 0) { 572192506Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 573192506Syongari NGE_SETBIT(sc, NGE_TX_CFG, 574192506Syongari (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 575101540Sambrisko NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 576192506Syongari#ifdef notyet 577192506Syongari /* Enable flow-control. */ 578192506Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 579192506Syongari (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0) 580192506Syongari NGE_SETBIT(sc, NGE_PAUSECSR, 581192506Syongari NGE_PAUSECSR_PAUSE_ENB); 582192506Syongari#endif 583101540Sambrisko } else { 584101540Sambrisko NGE_CLRBIT(sc, NGE_TX_CFG, 585192506Syongari (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 586101540Sambrisko NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 587192506Syongari NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB); 588101540Sambrisko } 589101540Sambrisko /* If we have a 1000Mbps link, set the mode_1000 bit. */ 590192506Syongari reg = CSR_READ_4(sc, NGE_CFG); 591192506Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 592192506Syongari case IFM_1000_SX: 593192506Syongari case IFM_1000_LX: 594192506Syongari case IFM_1000_CX: 595192506Syongari case IFM_1000_T: 596192506Syongari reg |= NGE_CFG_MODE_1000; 597192506Syongari break; 598192506Syongari default: 599192506Syongari reg &= ~NGE_CFG_MODE_1000; 600192506Syongari break; 601101540Sambrisko } 602192506Syongari CSR_WRITE_4(sc, NGE_CFG, reg); 603192506Syongari 604192506Syongari /* Reset Tx/Rx MAC. */ 605192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 606192506Syongari reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET; 607192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 608192506Syongari /* Check the completion of reset. */ 609192506Syongari done = 0; 610192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 611192506Syongari DELAY(1); 612192506Syongari status = CSR_READ_4(sc, NGE_ISR); 613192506Syongari if ((status & NGE_ISR_RX_RESET_DONE) != 0) 614192506Syongari done |= NGE_ISR_RX_RESET_DONE; 615192506Syongari if ((status & NGE_ISR_TX_RESET_DONE) != 0) 616192506Syongari done |= NGE_ISR_TX_RESET_DONE; 617192506Syongari if (done == 618192506Syongari (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE)) 619192506Syongari break; 620192506Syongari } 621192506Syongari if (i == NGE_TIMEOUT) 622192506Syongari device_printf(sc->nge_dev, 623192506Syongari "%s: unable to reset Tx/Rx MAC\n", __func__); 624192506Syongari /* Reuse Rx buffer and reset consumer pointer. */ 625192506Syongari sc->nge_cdata.nge_rx_cons = 0; 626192506Syongari /* 627192506Syongari * It seems that resetting Rx/Tx MAC results in 628192506Syongari * resetting Tx/Rx descriptor pointer registers such 629192506Syongari * that reloading Tx/Rx lists address are needed. 630192506Syongari */ 631192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 632192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 633192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 634192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 635192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 636192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 637192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 638192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 639192506Syongari /* Reinitialize Tx buffers. */ 640192506Syongari nge_list_tx_init(sc); 641192506Syongari 642192506Syongari /* Restart Rx MAC. */ 643192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 644192506Syongari reg |= NGE_CSR_RX_ENABLE; 645192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 646192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 647192506Syongari if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0) 648192506Syongari break; 649192506Syongari DELAY(1); 650192506Syongari } 651192506Syongari if (i == NGE_TIMEOUT) 652192506Syongari device_printf(sc->nge_dev, 653192506Syongari "%s: unable to restart Rx MAC\n", __func__); 65479424Swpaul } 655192506Syongari 656192506Syongari /* Data LED off for TBI mode */ 657192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 658192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 659192506Syongari CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 66076479Swpaul} 66176479Swpaul 66299497Salfredstatic void 663192506Syongaringe_rxfilter(struct nge_softc *sc) 66476479Swpaul{ 665192297Syongari struct ifnet *ifp; 666192297Syongari struct ifmultiaddr *ifma; 667192506Syongari uint32_t h, i, rxfilt; 668192297Syongari int bit, index; 66976479Swpaul 670135250Swpaul NGE_LOCK_ASSERT(sc); 671147256Sbrooks ifp = sc->nge_ifp; 67276479Swpaul 673192506Syongari /* Make sure to stop Rx filtering. */ 674192506Syongari rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL); 675192506Syongari rxfilt &= ~NGE_RXFILTCTL_ENABLE; 676192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 677226995Smarius CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 678192506Syongari 679192506Syongari rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS); 680192506Syongari rxfilt &= ~NGE_RXFILTCTL_BROAD; 681192506Syongari /* 682192506Syongari * We don't want to use the hash table for matching unicast 683192506Syongari * addresses. 684192506Syongari */ 685192506Syongari rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 686192506Syongari 687192506Syongari /* 688192506Syongari * For the NatSemi chip, we have to explicitly enable the 689192506Syongari * reception of ARP frames, as well as turn on the 'perfect 690192506Syongari * match' filter where we store the station address, otherwise 691192506Syongari * we won't receive unicasts meant for this host. 692192506Syongari */ 693192506Syongari rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT; 694192506Syongari 695192506Syongari /* 696192506Syongari * Set the capture broadcast bit to capture broadcast frames. 697192506Syongari */ 698192506Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 699192506Syongari rxfilt |= NGE_RXFILTCTL_BROAD; 700192506Syongari 701192506Syongari if ((ifp->if_flags & IFF_PROMISC) != 0 || 702192506Syongari (ifp->if_flags & IFF_ALLMULTI) != 0) { 703192506Syongari rxfilt |= NGE_RXFILTCTL_ALLMULTI; 704192506Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 705192506Syongari rxfilt |= NGE_RXFILTCTL_ALLPHYS; 706192506Syongari goto done; 70776479Swpaul } 70876479Swpaul 70976479Swpaul /* 71076479Swpaul * We have to explicitly enable the multicast hash table 71176479Swpaul * on the NatSemi chip if we want to use it, which we do. 71276479Swpaul */ 713192506Syongari rxfilt |= NGE_RXFILTCTL_MCHASH; 71476479Swpaul 71576479Swpaul /* first, zot all the existing hash bits */ 71676479Swpaul for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 71776479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 71876479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 71976479Swpaul } 72076479Swpaul 72176479Swpaul /* 72276479Swpaul * From the 11 bits returned by the crc routine, the top 7 72376479Swpaul * bits represent the 16-bit word in the mcast hash table 72476479Swpaul * that needs to be updated, and the lower 4 bits represent 72576479Swpaul * which bit within that byte needs to be set. 72676479Swpaul */ 727195049Srwatson if_maddr_rlock(ifp); 72876479Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 72976479Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 73076479Swpaul continue; 731130270Snaddy h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 732130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 73376479Swpaul index = (h >> 4) & 0x7F; 73476479Swpaul bit = h & 0xF; 73576479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, 73676479Swpaul NGE_FILTADDR_MCAST_LO + (index * 2)); 73776479Swpaul NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 73876479Swpaul } 739195049Srwatson if_maddr_runlock(ifp); 74076479Swpaul 741192506Syongaridone: 742192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 743192506Syongari /* Turn the receive filter on. */ 744192506Syongari rxfilt |= NGE_RXFILTCTL_ENABLE; 745192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 746226995Smarius CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 74776479Swpaul} 74876479Swpaul 74999497Salfredstatic void 750192288Syongaringe_reset(struct nge_softc *sc) 75176479Swpaul{ 752192506Syongari uint32_t v; 753192297Syongari int i; 75476479Swpaul 75576479Swpaul NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 75676479Swpaul 75776479Swpaul for (i = 0; i < NGE_TIMEOUT; i++) { 75876479Swpaul if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 75976479Swpaul break; 760192506Syongari DELAY(1); 76176479Swpaul } 76276479Swpaul 76376479Swpaul if (i == NGE_TIMEOUT) 764162321Sglebius device_printf(sc->nge_dev, "reset never completed\n"); 76576479Swpaul 76676479Swpaul /* Wait a little while for the chip to get its brains in order. */ 76776479Swpaul DELAY(1000); 76876479Swpaul 76976479Swpaul /* 77076479Swpaul * If this is a NetSemi chip, make sure to clear 77176479Swpaul * PME mode. 77276479Swpaul */ 77376479Swpaul CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 77476479Swpaul CSR_WRITE_4(sc, NGE_CLKRUN, 0); 775192506Syongari 776192506Syongari /* Clear WOL events which may interfere normal Rx filter opertaion. */ 777192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, 0); 778192506Syongari 779192506Syongari /* 780192506Syongari * Only DP83820 supports 64bits addressing/data transfers and 781192506Syongari * 64bit addressing requires different descriptor structures. 782192506Syongari * To make it simple, disable 64bit addressing/data transfers. 783192506Syongari */ 784192506Syongari v = CSR_READ_4(sc, NGE_CFG); 785192506Syongari v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB); 786192506Syongari CSR_WRITE_4(sc, NGE_CFG, v); 78776479Swpaul} 78876479Swpaul 78976479Swpaul/* 790108470Sschweikh * Probe for a NatSemi chip. Check the PCI vendor and device 79176479Swpaul * IDs against our list and return a device name if we find a match. 79276479Swpaul */ 79399497Salfredstatic int 794192288Syongaringe_probe(device_t dev) 79576479Swpaul{ 796226995Smarius const struct nge_type *t; 79776479Swpaul 79876479Swpaul t = nge_devs; 79976479Swpaul 800192292Syongari while (t->nge_name != NULL) { 80176479Swpaul if ((pci_get_vendor(dev) == t->nge_vid) && 80276479Swpaul (pci_get_device(dev) == t->nge_did)) { 80376479Swpaul device_set_desc(dev, t->nge_name); 804192292Syongari return (BUS_PROBE_DEFAULT); 80576479Swpaul } 80676479Swpaul t++; 80776479Swpaul } 80876479Swpaul 809192292Syongari return (ENXIO); 81076479Swpaul} 81176479Swpaul 81276479Swpaul/* 81376479Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81476479Swpaul * setup and ethernet/BPF attach. 81576479Swpaul */ 81699497Salfredstatic int 817192288Syongaringe_attach(device_t dev) 81876479Swpaul{ 819192506Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 820192506Syongari uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg; 821192297Syongari struct nge_softc *sc; 822192506Syongari struct ifnet *ifp; 823192506Syongari int error, i, rid; 82476479Swpaul 825192506Syongari error = 0; 82676479Swpaul sc = device_get_softc(dev); 827162321Sglebius sc->nge_dev = dev; 82876479Swpaul 829135250Swpaul NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 830151296Sjhb callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0); 831151296Sjhb 83276479Swpaul /* 83376479Swpaul * Map control/status registers. 83476479Swpaul */ 83576479Swpaul pci_enable_busmaster(dev); 83676479Swpaul 837192506Syongari#ifdef NGE_USEIOSPACE 838192506Syongari sc->nge_res_type = SYS_RES_IOPORT; 839192506Syongari sc->nge_res_id = PCIR_BAR(0); 840192506Syongari#else 841192506Syongari sc->nge_res_type = SYS_RES_MEMORY; 842192506Syongari sc->nge_res_id = PCIR_BAR(1); 843192506Syongari#endif 844192506Syongari sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 845192506Syongari &sc->nge_res_id, RF_ACTIVE); 84676479Swpaul 84776479Swpaul if (sc->nge_res == NULL) { 848192506Syongari if (sc->nge_res_type == SYS_RES_MEMORY) { 849192506Syongari sc->nge_res_type = SYS_RES_IOPORT; 850192506Syongari sc->nge_res_id = PCIR_BAR(0); 851192506Syongari } else { 852192506Syongari sc->nge_res_type = SYS_RES_MEMORY; 853192506Syongari sc->nge_res_id = PCIR_BAR(1); 854192506Syongari } 855192506Syongari sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 856192506Syongari &sc->nge_res_id, RF_ACTIVE); 857192506Syongari if (sc->nge_res == NULL) { 858192506Syongari device_printf(dev, "couldn't allocate %s resources\n", 859192506Syongari sc->nge_res_type == SYS_RES_MEMORY ? "memory" : 860192506Syongari "I/O"); 861192506Syongari NGE_LOCK_DESTROY(sc); 862192506Syongari return (ENXIO); 863192506Syongari } 86476479Swpaul } 86576479Swpaul 86676479Swpaul /* Allocate interrupt */ 86776479Swpaul rid = 0; 868127135Snjl sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 86976479Swpaul RF_SHAREABLE | RF_ACTIVE); 87076479Swpaul 87176479Swpaul if (sc->nge_irq == NULL) { 872151296Sjhb device_printf(dev, "couldn't map interrupt\n"); 87376479Swpaul error = ENXIO; 87476479Swpaul goto fail; 87576479Swpaul } 87676479Swpaul 877192506Syongari /* Enable MWI. */ 878192506Syongari reg = pci_read_config(dev, PCIR_COMMAND, 2); 879192506Syongari reg |= PCIM_CMD_MWRICEN; 880192506Syongari pci_write_config(dev, PCIR_COMMAND, reg, 2); 881192506Syongari 88276479Swpaul /* Reset the adapter. */ 88376479Swpaul nge_reset(sc); 88476479Swpaul 88576479Swpaul /* 88676479Swpaul * Get station address from the EEPROM. 88776479Swpaul */ 888192506Syongari nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3); 889192506Syongari for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 890192506Syongari ea[i] = le16toh(ea[i]); 891192506Syongari ea_temp = ea[0]; 892192506Syongari ea[0] = ea[2]; 893192506Syongari ea[2] = ea_temp; 894192506Syongari bcopy(ea, eaddr, sizeof(eaddr)); 89576479Swpaul 896192506Syongari if (nge_dma_alloc(sc) != 0) { 89776479Swpaul error = ENXIO; 89876479Swpaul goto fail; 89976479Swpaul } 90076479Swpaul 901192506Syongari nge_sysctl_node(sc); 902192506Syongari 903147256Sbrooks ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 904147256Sbrooks if (ifp == NULL) { 905192506Syongari device_printf(dev, "can not allocate ifnet structure\n"); 906147256Sbrooks error = ENOSPC; 907147256Sbrooks goto fail; 908147256Sbrooks } 90976479Swpaul ifp->if_softc = sc; 910121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 911135250Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 91276479Swpaul ifp->if_ioctl = nge_ioctl; 91376479Swpaul ifp->if_start = nge_start; 91476479Swpaul ifp->if_init = nge_init; 915192506Syongari ifp->if_snd.ifq_drv_maxlen = NGE_TX_RING_CNT - 1; 916192506Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 917192506Syongari IFQ_SET_READY(&ifp->if_snd); 91876479Swpaul ifp->if_hwassist = NGE_CSUM_FEATURES; 919192506Syongari ifp->if_capabilities = IFCAP_HWCSUM; 920192506Syongari /* 921192506Syongari * It seems that some hardwares doesn't provide 3.3V auxiliary 922192506Syongari * supply(3VAUX) to drive PME such that checking PCI power 923192506Syongari * management capability is necessary. 924192506Syongari */ 925219902Sjhb if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0) 926192506Syongari ifp->if_capabilities |= IFCAP_WOL; 927150789Sglebius ifp->if_capenable = ifp->if_capabilities; 92876479Swpaul 929192506Syongari if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) { 930192506Syongari sc->nge_flags |= NGE_FLAG_TBI; 931192506Syongari device_printf(dev, "Using TBI\n"); 932192506Syongari /* Configure GPIO. */ 933192506Syongari CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 934192506Syongari | NGE_GPIO_GP4_OUT 935192506Syongari | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 936192506Syongari | NGE_GPIO_GP3_OUTENB 937192506Syongari | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 938192506Syongari } 939192506Syongari 94076479Swpaul /* 94176479Swpaul * Do MII setup. 94276479Swpaul */ 943213894Smarius error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange, 944213894Smarius nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 945192506Syongari if (error != 0) { 946213894Smarius device_printf(dev, "attaching PHYs failed\n"); 947192506Syongari goto fail; 94876479Swpaul } 94976479Swpaul 95076479Swpaul /* 95176479Swpaul * Call MI attach routine. 95276479Swpaul */ 953106937Ssam ether_ifattach(ifp, eaddr); 95476479Swpaul 955192506Syongari /* VLAN capability setup. */ 956192506Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 957192506Syongari ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 958192506Syongari ifp->if_capenable = ifp->if_capabilities; 959192506Syongari#ifdef DEVICE_POLLING 960192506Syongari ifp->if_capabilities |= IFCAP_POLLING; 961192506Syongari#endif 962135250Swpaul /* 963192506Syongari * Tell the upper layer(s) we support long frames. 964192506Syongari * Must appear after the call to ether_ifattach() because 965192506Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 966192506Syongari */ 967270856Sglebius ifp->if_hdrlen = sizeof(struct ether_vlan_header); 968192506Syongari 969192506Syongari /* 970135250Swpaul * Hookup IRQ last. 971135250Swpaul */ 972135250Swpaul error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 973166901Spiso NULL, nge_intr, sc, &sc->nge_intrhand); 974135250Swpaul if (error) { 975151296Sjhb device_printf(dev, "couldn't set up irq\n"); 976151296Sjhb goto fail; 977151296Sjhb } 978151296Sjhb 979151296Sjhbfail: 980192506Syongari if (error != 0) 981192506Syongari nge_detach(dev); 982192292Syongari return (error); 98376479Swpaul} 98476479Swpaul 98599497Salfredstatic int 986192288Syongaringe_detach(device_t dev) 98776479Swpaul{ 988192297Syongari struct nge_softc *sc; 989192297Syongari struct ifnet *ifp; 99076479Swpaul 99176479Swpaul sc = device_get_softc(dev); 992147256Sbrooks ifp = sc->nge_ifp; 99376479Swpaul 994150789Sglebius#ifdef DEVICE_POLLING 995192506Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 996150789Sglebius ether_poll_deregister(ifp); 997150789Sglebius#endif 99876479Swpaul 999192506Syongari if (device_is_attached(dev)) { 1000192506Syongari NGE_LOCK(sc); 1001192506Syongari sc->nge_flags |= NGE_FLAG_DETACH; 1002192506Syongari nge_stop(sc); 1003192506Syongari NGE_UNLOCK(sc); 1004192506Syongari callout_drain(&sc->nge_stat_ch); 1005192506Syongari if (ifp != NULL) 1006192506Syongari ether_ifdetach(ifp); 1007192506Syongari } 1008192506Syongari 1009192506Syongari if (sc->nge_miibus != NULL) { 1010101540Sambrisko device_delete_child(dev, sc->nge_miibus); 1011192506Syongari sc->nge_miibus = NULL; 1012101540Sambrisko } 1013192506Syongari bus_generic_detach(dev); 1014192506Syongari if (sc->nge_intrhand != NULL) 1015192506Syongari bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1016192506Syongari if (sc->nge_irq != NULL) 1017192506Syongari bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1018192506Syongari if (sc->nge_res != NULL) 1019192506Syongari bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id, 1020192506Syongari sc->nge_res); 102176479Swpaul 1022192506Syongari nge_dma_free(sc); 1023192506Syongari if (ifp != NULL) 1024192506Syongari if_free(ifp); 102576479Swpaul 1026135251Swpaul NGE_LOCK_DESTROY(sc); 1027135251Swpaul 1028192292Syongari return (0); 102976479Swpaul} 103076479Swpaul 1031192506Syongaristruct nge_dmamap_arg { 1032192506Syongari bus_addr_t nge_busaddr; 1033192506Syongari}; 1034192506Syongari 1035192506Syongaristatic void 1036192506Syongaringe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1037192506Syongari{ 1038192506Syongari struct nge_dmamap_arg *ctx; 1039192506Syongari 1040192506Syongari if (error != 0) 1041192506Syongari return; 1042192506Syongari ctx = arg; 1043192506Syongari ctx->nge_busaddr = segs[0].ds_addr; 1044192506Syongari} 1045192506Syongari 1046192506Syongaristatic int 1047192506Syongaringe_dma_alloc(struct nge_softc *sc) 1048192506Syongari{ 1049192506Syongari struct nge_dmamap_arg ctx; 1050192506Syongari struct nge_txdesc *txd; 1051192506Syongari struct nge_rxdesc *rxd; 1052192506Syongari int error, i; 1053192506Syongari 1054192506Syongari /* Create parent DMA tag. */ 1055192506Syongari error = bus_dma_tag_create( 1056192506Syongari bus_get_dma_tag(sc->nge_dev), /* parent */ 1057192506Syongari 1, 0, /* alignment, boundary */ 1058192506Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1059192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1060192506Syongari NULL, NULL, /* filter, filterarg */ 1061192506Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1062192506Syongari 0, /* nsegments */ 1063192506Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1064192506Syongari 0, /* flags */ 1065192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1066192506Syongari &sc->nge_cdata.nge_parent_tag); 1067192506Syongari if (error != 0) { 1068192506Syongari device_printf(sc->nge_dev, "failed to create parent DMA tag\n"); 1069192506Syongari goto fail; 1070192506Syongari } 1071192506Syongari /* Create tag for Tx ring. */ 1072192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1073192506Syongari NGE_RING_ALIGN, 0, /* alignment, boundary */ 1074192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1075192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1076192506Syongari NULL, NULL, /* filter, filterarg */ 1077192506Syongari NGE_TX_RING_SIZE, /* maxsize */ 1078192506Syongari 1, /* nsegments */ 1079192506Syongari NGE_TX_RING_SIZE, /* maxsegsize */ 1080192506Syongari 0, /* flags */ 1081192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1082192506Syongari &sc->nge_cdata.nge_tx_ring_tag); 1083192506Syongari if (error != 0) { 1084192506Syongari device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n"); 1085192506Syongari goto fail; 1086192506Syongari } 1087192506Syongari 1088192506Syongari /* Create tag for Rx ring. */ 1089192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1090192506Syongari NGE_RING_ALIGN, 0, /* alignment, boundary */ 1091192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1092192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1093192506Syongari NULL, NULL, /* filter, filterarg */ 1094192506Syongari NGE_RX_RING_SIZE, /* maxsize */ 1095192506Syongari 1, /* nsegments */ 1096192506Syongari NGE_RX_RING_SIZE, /* maxsegsize */ 1097192506Syongari 0, /* flags */ 1098192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1099192506Syongari &sc->nge_cdata.nge_rx_ring_tag); 1100192506Syongari if (error != 0) { 1101192506Syongari device_printf(sc->nge_dev, 1102192506Syongari "failed to create Rx ring DMA tag\n"); 1103192506Syongari goto fail; 1104192506Syongari } 1105192506Syongari 1106192506Syongari /* Create tag for Tx buffers. */ 1107192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1108192506Syongari 1, 0, /* alignment, boundary */ 1109192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1110192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1111192506Syongari NULL, NULL, /* filter, filterarg */ 1112192506Syongari MCLBYTES * NGE_MAXTXSEGS, /* maxsize */ 1113192506Syongari NGE_MAXTXSEGS, /* nsegments */ 1114192506Syongari MCLBYTES, /* maxsegsize */ 1115192506Syongari 0, /* flags */ 1116192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1117192506Syongari &sc->nge_cdata.nge_tx_tag); 1118192506Syongari if (error != 0) { 1119192506Syongari device_printf(sc->nge_dev, "failed to create Tx DMA tag\n"); 1120192506Syongari goto fail; 1121192506Syongari } 1122192506Syongari 1123192506Syongari /* Create tag for Rx buffers. */ 1124192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1125192506Syongari NGE_RX_ALIGN, 0, /* alignment, boundary */ 1126192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1127192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1128192506Syongari NULL, NULL, /* filter, filterarg */ 1129192506Syongari MCLBYTES, /* maxsize */ 1130192506Syongari 1, /* nsegments */ 1131192506Syongari MCLBYTES, /* maxsegsize */ 1132192506Syongari 0, /* flags */ 1133192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1134192506Syongari &sc->nge_cdata.nge_rx_tag); 1135192506Syongari if (error != 0) { 1136192506Syongari device_printf(sc->nge_dev, "failed to create Rx DMA tag\n"); 1137192506Syongari goto fail; 1138192506Syongari } 1139192506Syongari 1140192506Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1141192506Syongari error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag, 1142192506Syongari (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK | 1143192506Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map); 1144192506Syongari if (error != 0) { 1145192506Syongari device_printf(sc->nge_dev, 1146192506Syongari "failed to allocate DMA'able memory for Tx ring\n"); 1147192506Syongari goto fail; 1148192506Syongari } 1149192506Syongari 1150192506Syongari ctx.nge_busaddr = 0; 1151192506Syongari error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag, 1152192506Syongari sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring, 1153192506Syongari NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1154192506Syongari if (error != 0 || ctx.nge_busaddr == 0) { 1155192506Syongari device_printf(sc->nge_dev, 1156192506Syongari "failed to load DMA'able memory for Tx ring\n"); 1157192506Syongari goto fail; 1158192506Syongari } 1159192506Syongari sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr; 1160192506Syongari 1161192506Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1162192506Syongari error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag, 1163192506Syongari (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK | 1164192506Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map); 1165192506Syongari if (error != 0) { 1166192506Syongari device_printf(sc->nge_dev, 1167192506Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1168192506Syongari goto fail; 1169192506Syongari } 1170192506Syongari 1171192506Syongari ctx.nge_busaddr = 0; 1172192506Syongari error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag, 1173192506Syongari sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring, 1174192506Syongari NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1175192506Syongari if (error != 0 || ctx.nge_busaddr == 0) { 1176192506Syongari device_printf(sc->nge_dev, 1177192506Syongari "failed to load DMA'able memory for Rx ring\n"); 1178192506Syongari goto fail; 1179192506Syongari } 1180192506Syongari sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr; 1181192506Syongari 1182192506Syongari /* Create DMA maps for Tx buffers. */ 1183192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1184192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1185192506Syongari txd->tx_m = NULL; 1186192506Syongari txd->tx_dmamap = NULL; 1187192506Syongari error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0, 1188192506Syongari &txd->tx_dmamap); 1189192506Syongari if (error != 0) { 1190192506Syongari device_printf(sc->nge_dev, 1191192506Syongari "failed to create Tx dmamap\n"); 1192192506Syongari goto fail; 1193192506Syongari } 1194192506Syongari } 1195192506Syongari /* Create DMA maps for Rx buffers. */ 1196192506Syongari if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1197192506Syongari &sc->nge_cdata.nge_rx_sparemap)) != 0) { 1198192506Syongari device_printf(sc->nge_dev, 1199192506Syongari "failed to create spare Rx dmamap\n"); 1200192506Syongari goto fail; 1201192506Syongari } 1202192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1203192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 1204192506Syongari rxd->rx_m = NULL; 1205192506Syongari rxd->rx_dmamap = NULL; 1206192506Syongari error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1207192506Syongari &rxd->rx_dmamap); 1208192506Syongari if (error != 0) { 1209192506Syongari device_printf(sc->nge_dev, 1210192506Syongari "failed to create Rx dmamap\n"); 1211192506Syongari goto fail; 1212192506Syongari } 1213192506Syongari } 1214192506Syongari 1215192506Syongarifail: 1216192506Syongari return (error); 1217192506Syongari} 1218192506Syongari 1219192506Syongaristatic void 1220192506Syongaringe_dma_free(struct nge_softc *sc) 1221192506Syongari{ 1222192506Syongari struct nge_txdesc *txd; 1223192506Syongari struct nge_rxdesc *rxd; 1224192506Syongari int i; 1225192506Syongari 1226192506Syongari /* Tx ring. */ 1227192506Syongari if (sc->nge_cdata.nge_tx_ring_tag) { 1228267363Sjhb if (sc->nge_rdata.nge_tx_ring_paddr) 1229192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag, 1230192506Syongari sc->nge_cdata.nge_tx_ring_map); 1231267363Sjhb if (sc->nge_rdata.nge_tx_ring) 1232192506Syongari bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag, 1233192506Syongari sc->nge_rdata.nge_tx_ring, 1234192506Syongari sc->nge_cdata.nge_tx_ring_map); 1235192506Syongari sc->nge_rdata.nge_tx_ring = NULL; 1236267363Sjhb sc->nge_rdata.nge_tx_ring_paddr = 0; 1237192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag); 1238192506Syongari sc->nge_cdata.nge_tx_ring_tag = NULL; 1239192506Syongari } 1240192506Syongari /* Rx ring. */ 1241192506Syongari if (sc->nge_cdata.nge_rx_ring_tag) { 1242267363Sjhb if (sc->nge_rdata.nge_rx_ring_paddr) 1243192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag, 1244192506Syongari sc->nge_cdata.nge_rx_ring_map); 1245267363Sjhb if (sc->nge_rdata.nge_rx_ring) 1246192506Syongari bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag, 1247192506Syongari sc->nge_rdata.nge_rx_ring, 1248192506Syongari sc->nge_cdata.nge_rx_ring_map); 1249192506Syongari sc->nge_rdata.nge_rx_ring = NULL; 1250267363Sjhb sc->nge_rdata.nge_rx_ring_paddr = 0; 1251192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag); 1252192506Syongari sc->nge_cdata.nge_rx_ring_tag = NULL; 1253192506Syongari } 1254192506Syongari /* Tx buffers. */ 1255192506Syongari if (sc->nge_cdata.nge_tx_tag) { 1256192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1257192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1258192506Syongari if (txd->tx_dmamap) { 1259192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag, 1260192506Syongari txd->tx_dmamap); 1261192506Syongari txd->tx_dmamap = NULL; 1262192506Syongari } 1263192506Syongari } 1264192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag); 1265192506Syongari sc->nge_cdata.nge_tx_tag = NULL; 1266192506Syongari } 1267192506Syongari /* Rx buffers. */ 1268192506Syongari if (sc->nge_cdata.nge_rx_tag) { 1269192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1270192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 1271192506Syongari if (rxd->rx_dmamap) { 1272192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1273192506Syongari rxd->rx_dmamap); 1274192506Syongari rxd->rx_dmamap = NULL; 1275192506Syongari } 1276192506Syongari } 1277192506Syongari if (sc->nge_cdata.nge_rx_sparemap) { 1278192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1279192506Syongari sc->nge_cdata.nge_rx_sparemap); 1280192506Syongari sc->nge_cdata.nge_rx_sparemap = 0; 1281192506Syongari } 1282192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag); 1283192506Syongari sc->nge_cdata.nge_rx_tag = NULL; 1284192506Syongari } 1285192506Syongari 1286192506Syongari if (sc->nge_cdata.nge_parent_tag) { 1287192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag); 1288192506Syongari sc->nge_cdata.nge_parent_tag = NULL; 1289192506Syongari } 1290192506Syongari} 1291192506Syongari 129276479Swpaul/* 129376479Swpaul * Initialize the transmit descriptors. 129476479Swpaul */ 129599497Salfredstatic int 1296192288Syongaringe_list_tx_init(struct nge_softc *sc) 129776479Swpaul{ 1298192506Syongari struct nge_ring_data *rd; 1299192506Syongari struct nge_txdesc *txd; 1300192506Syongari bus_addr_t addr; 1301192297Syongari int i; 130276479Swpaul 1303192506Syongari sc->nge_cdata.nge_tx_prod = 0; 1304192506Syongari sc->nge_cdata.nge_tx_cons = 0; 1305192506Syongari sc->nge_cdata.nge_tx_cnt = 0; 130676479Swpaul 1307192506Syongari rd = &sc->nge_rdata; 1308192506Syongari bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT); 1309192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1310192506Syongari if (i == NGE_TX_RING_CNT - 1) 1311192506Syongari addr = NGE_TX_RING_ADDR(sc, 0); 1312192506Syongari else 1313192506Syongari addr = NGE_TX_RING_ADDR(sc, i + 1); 1314192506Syongari rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1315192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1316192506Syongari txd->tx_m = NULL; 131776479Swpaul } 131876479Swpaul 1319192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1320192506Syongari sc->nge_cdata.nge_tx_ring_map, 1321192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 132276479Swpaul 1323192292Syongari return (0); 132476479Swpaul} 132576479Swpaul 132676479Swpaul/* 132776479Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 132876479Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 132976479Swpaul * points back to the first. 133076479Swpaul */ 133199497Salfredstatic int 1332192288Syongaringe_list_rx_init(struct nge_softc *sc) 133376479Swpaul{ 1334192506Syongari struct nge_ring_data *rd; 1335192506Syongari bus_addr_t addr; 1336192297Syongari int i; 133776479Swpaul 1338192506Syongari sc->nge_cdata.nge_rx_cons = 0; 1339192506Syongari sc->nge_head = sc->nge_tail = NULL; 134076479Swpaul 1341192506Syongari rd = &sc->nge_rdata; 1342192506Syongari bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT); 1343192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1344192506Syongari if (nge_newbuf(sc, i) != 0) 1345192292Syongari return (ENOBUFS); 1346192506Syongari if (i == NGE_RX_RING_CNT - 1) 1347192506Syongari addr = NGE_RX_RING_ADDR(sc, 0); 1348192506Syongari else 1349192506Syongari addr = NGE_RX_RING_ADDR(sc, i + 1); 1350192506Syongari rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 135176479Swpaul } 135276479Swpaul 1353192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1354192506Syongari sc->nge_cdata.nge_rx_ring_map, 1355192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 135676479Swpaul 1357192292Syongari return (0); 135876479Swpaul} 135976479Swpaul 1360192506Syongaristatic __inline void 1361192506Syongaringe_discard_rxbuf(struct nge_softc *sc, int idx) 1362192506Syongari{ 1363192506Syongari struct nge_desc *desc; 1364192506Syongari 1365192506Syongari desc = &sc->nge_rdata.nge_rx_ring[idx]; 1366192506Syongari desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t)); 1367192506Syongari desc->nge_extsts = 0; 1368192506Syongari} 1369192506Syongari 137076479Swpaul/* 137176479Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 137276479Swpaul */ 137399497Salfredstatic int 1374192506Syongaringe_newbuf(struct nge_softc *sc, int idx) 137576479Swpaul{ 1376192506Syongari struct nge_desc *desc; 1377192506Syongari struct nge_rxdesc *rxd; 1378192506Syongari struct mbuf *m; 1379192506Syongari bus_dma_segment_t segs[1]; 1380192506Syongari bus_dmamap_t map; 1381192506Syongari int nsegs; 138276479Swpaul 1383243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1384192506Syongari if (m == NULL) 1385192506Syongari return (ENOBUFS); 1386135250Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 1387192294Syongari m_adj(m, sizeof(uint64_t)); 138876479Swpaul 1389192506Syongari if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag, 1390192506Syongari sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1391192506Syongari m_freem(m); 1392192506Syongari return (ENOBUFS); 1393192506Syongari } 1394192506Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 139576479Swpaul 1396192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[idx]; 1397192506Syongari if (rxd->rx_m != NULL) { 1398192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1399192506Syongari BUS_DMASYNC_POSTREAD); 1400192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap); 1401192506Syongari } 1402192506Syongari map = rxd->rx_dmamap; 1403192506Syongari rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap; 1404192506Syongari sc->nge_cdata.nge_rx_sparemap = map; 1405192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1406192506Syongari BUS_DMASYNC_PREREAD); 1407192506Syongari rxd->rx_m = m; 1408192506Syongari desc = &sc->nge_rdata.nge_rx_ring[idx]; 1409192506Syongari desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr)); 1410192506Syongari desc->nge_cmdsts = htole32(segs[0].ds_len); 1411192506Syongari desc->nge_extsts = 0; 1412192506Syongari 1413192292Syongari return (0); 141476479Swpaul} 141576479Swpaul 1416192506Syongari#ifndef __NO_STRICT_ALIGNMENT 1417135250Swpaulstatic __inline void 1418192288Syongaringe_fixup_rx(struct mbuf *m) 1419192290Syongari{ 1420192506Syongari int i; 1421192506Syongari uint16_t *src, *dst; 1422192290Syongari 1423135250Swpaul src = mtod(m, uint16_t *); 1424135250Swpaul dst = src - 1; 1425192290Syongari 1426135250Swpaul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1427135250Swpaul *dst++ = *src++; 1428192290Syongari 1429135250Swpaul m->m_data -= ETHER_ALIGN; 1430192290Syongari} 143176479Swpaul#endif 143276479Swpaul 143376479Swpaul/* 143476479Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 143576479Swpaul * the higher level protocols. 143676479Swpaul */ 1437193105Sattiliostatic int 1438192288Syongaringe_rxeof(struct nge_softc *sc) 143976479Swpaul{ 1440192298Syongari struct mbuf *m; 1441192298Syongari struct ifnet *ifp; 1442192297Syongari struct nge_desc *cur_rx; 1443192506Syongari struct nge_rxdesc *rxd; 1444193105Sattilio int cons, prog, rx_npkts, total_len; 1445192506Syongari uint32_t cmdsts, extsts; 144676479Swpaul 1447135250Swpaul NGE_LOCK_ASSERT(sc); 1448192506Syongari 1449147256Sbrooks ifp = sc->nge_ifp; 1450192506Syongari cons = sc->nge_cdata.nge_rx_cons; 1451193105Sattilio rx_npkts = 0; 145276479Swpaul 1453192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1454192506Syongari sc->nge_cdata.nge_rx_ring_map, 1455192506Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 145676479Swpaul 1457192506Syongari for (prog = 0; prog < NGE_RX_RING_CNT && 1458192506Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1459192506Syongari NGE_INC(cons, NGE_RX_RING_CNT)) { 1460106507Ssimokawa#ifdef DEVICE_POLLING 1461150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1462106507Ssimokawa if (sc->rxcycles <= 0) 1463106507Ssimokawa break; 1464106507Ssimokawa sc->rxcycles--; 1465106507Ssimokawa } 1466150789Sglebius#endif 1467192506Syongari cur_rx = &sc->nge_rdata.nge_rx_ring[cons]; 1468192506Syongari cmdsts = le32toh(cur_rx->nge_cmdsts); 1469192506Syongari extsts = le32toh(cur_rx->nge_extsts); 1470192506Syongari if ((cmdsts & NGE_CMDSTS_OWN) == 0) 1471192506Syongari break; 1472192506Syongari prog++; 1473192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[cons]; 1474192506Syongari m = rxd->rx_m; 1475192506Syongari total_len = cmdsts & NGE_CMDSTS_BUFLEN; 1476106507Ssimokawa 1477192506Syongari if ((cmdsts & NGE_CMDSTS_MORE) != 0) { 1478192506Syongari if (nge_newbuf(sc, cons) != 0) { 1479271812Sglebius if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1480192506Syongari if (sc->nge_head != NULL) { 1481192506Syongari m_freem(sc->nge_head); 1482192506Syongari sc->nge_head = sc->nge_tail = NULL; 1483192506Syongari } 1484192506Syongari nge_discard_rxbuf(sc, cons); 1485192506Syongari continue; 1486192506Syongari } 1487135250Swpaul m->m_len = total_len; 1488135250Swpaul if (sc->nge_head == NULL) { 1489135250Swpaul m->m_pkthdr.len = total_len; 1490135250Swpaul sc->nge_head = sc->nge_tail = m; 1491135250Swpaul } else { 1492135250Swpaul m->m_flags &= ~M_PKTHDR; 1493135250Swpaul sc->nge_head->m_pkthdr.len += total_len; 1494135250Swpaul sc->nge_tail->m_next = m; 1495135250Swpaul sc->nge_tail = m; 1496135250Swpaul } 1497135250Swpaul continue; 1498135250Swpaul } 1499135250Swpaul 150076479Swpaul /* 150176479Swpaul * If an error occurs, update stats, clear the 150276479Swpaul * status word and leave the mbuf cluster in place: 150376479Swpaul * it should simply get re-used next time this descriptor 150476479Swpaul * comes up in the ring. 150576479Swpaul */ 1506192506Syongari if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1507192506Syongari if ((cmdsts & NGE_RXSTAT_RUNT) && 1508192506Syongari total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) { 1509192506Syongari /* 1510192506Syongari * Work-around hardware bug, accept runt frames 1511192506Syongari * if its length is larger than or equal to 56. 1512192506Syongari */ 1513192506Syongari } else { 1514192506Syongari /* 1515192506Syongari * Input error counters are updated by hardware. 1516192506Syongari */ 1517192506Syongari if (sc->nge_head != NULL) { 1518192506Syongari m_freem(sc->nge_head); 1519192506Syongari sc->nge_head = sc->nge_tail = NULL; 1520192506Syongari } 1521192506Syongari nge_discard_rxbuf(sc, cons); 1522192506Syongari continue; 1523135250Swpaul } 152476479Swpaul } 152576479Swpaul 1526135250Swpaul /* Try conjure up a replacement mbuf. */ 1527135250Swpaul 1528192506Syongari if (nge_newbuf(sc, cons) != 0) { 1529271812Sglebius if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1530135250Swpaul if (sc->nge_head != NULL) { 1531135250Swpaul m_freem(sc->nge_head); 1532135250Swpaul sc->nge_head = sc->nge_tail = NULL; 1533135250Swpaul } 1534192506Syongari nge_discard_rxbuf(sc, cons); 1535135250Swpaul continue; 1536135250Swpaul } 1537135250Swpaul 1538192506Syongari /* Chain received mbufs. */ 1539135250Swpaul if (sc->nge_head != NULL) { 1540135250Swpaul m->m_len = total_len; 1541135250Swpaul m->m_flags &= ~M_PKTHDR; 1542135250Swpaul sc->nge_tail->m_next = m; 1543135250Swpaul m = sc->nge_head; 1544135250Swpaul m->m_pkthdr.len += total_len; 1545135250Swpaul sc->nge_head = sc->nge_tail = NULL; 1546135250Swpaul } else 1547135250Swpaul m->m_pkthdr.len = m->m_len = total_len; 1548135250Swpaul 154976479Swpaul /* 155076479Swpaul * Ok. NatSemi really screwed up here. This is the 155176479Swpaul * only gigE chip I know of with alignment constraints 155276479Swpaul * on receive buffers. RX buffers must be 64-bit aligned. 155376479Swpaul */ 155479562Swpaul /* 155579562Swpaul * By popular demand, ignore the alignment problems 1556192506Syongari * on the non-strict alignment platform. The performance hit 155779562Swpaul * incurred due to unaligned accesses is much smaller 155879562Swpaul * than the hit produced by forcing buffer copies all 155979562Swpaul * the time, especially with jumbo frames. We still 156079562Swpaul * need to fix up the alignment everywhere else though. 156179562Swpaul */ 1562192506Syongari#ifndef __NO_STRICT_ALIGNMENT 1563135250Swpaul nge_fixup_rx(m); 156479562Swpaul#endif 1565192506Syongari m->m_pkthdr.rcvif = ifp; 1566271812Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 156776479Swpaul 1568192506Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1569192506Syongari /* Do IP checksum checking. */ 1570192506Syongari if ((extsts & NGE_RXEXTSTS_IPPKT) != 0) 1571192506Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1572192506Syongari if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0) 1573192506Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1574192506Syongari if ((extsts & NGE_RXEXTSTS_TCPPKT && 1575192506Syongari !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1576192506Syongari (extsts & NGE_RXEXTSTS_UDPPKT && 1577192506Syongari !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1578192506Syongari m->m_pkthdr.csum_flags |= 1579192506Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1580192506Syongari m->m_pkthdr.csum_data = 0xffff; 1581192506Syongari } 158278323Swpaul } 158376479Swpaul 158476479Swpaul /* 158576479Swpaul * If we received a packet with a vlan tag, pass it 158676479Swpaul * to vlan_input() instead of ether_input(). 158776479Swpaul */ 1588192506Syongari if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 && 1589192506Syongari (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1590162375Sandre m->m_pkthdr.ether_vtag = 1591192506Syongari bswap16(extsts & NGE_RXEXTSTS_VTCI); 1592162375Sandre m->m_flags |= M_VLANTAG; 1593106937Ssam } 1594135250Swpaul NGE_UNLOCK(sc); 1595106937Ssam (*ifp->if_input)(ifp, m); 1596135250Swpaul NGE_LOCK(sc); 1597193105Sattilio rx_npkts++; 159876479Swpaul } 159976479Swpaul 1600192506Syongari if (prog > 0) { 1601192506Syongari sc->nge_cdata.nge_rx_cons = cons; 1602192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1603192506Syongari sc->nge_cdata.nge_rx_ring_map, 1604192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1605192506Syongari } 1606193105Sattilio return (rx_npkts); 160776479Swpaul} 160876479Swpaul 160976479Swpaul/* 161076479Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 161176479Swpaul * the list buffers. 161276479Swpaul */ 161399497Salfredstatic void 1614192288Syongaringe_txeof(struct nge_softc *sc) 161576479Swpaul{ 1616192506Syongari struct nge_desc *cur_tx; 1617192506Syongari struct nge_txdesc *txd; 1618192297Syongari struct ifnet *ifp; 1619192506Syongari uint32_t cmdsts; 1620192506Syongari int cons, prod; 162176479Swpaul 1622135250Swpaul NGE_LOCK_ASSERT(sc); 1623147256Sbrooks ifp = sc->nge_ifp; 162476479Swpaul 1625192506Syongari cons = sc->nge_cdata.nge_tx_cons; 1626192506Syongari prod = sc->nge_cdata.nge_tx_prod; 1627192506Syongari if (cons == prod) 1628192506Syongari return; 1629192506Syongari 1630192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1631192506Syongari sc->nge_cdata.nge_tx_ring_map, 1632192506Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1633192506Syongari 163476479Swpaul /* 163576479Swpaul * Go through our tx list and free mbufs for those 163676479Swpaul * frames that have been transmitted. 163776479Swpaul */ 1638192506Syongari for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) { 1639192506Syongari cur_tx = &sc->nge_rdata.nge_tx_ring[cons]; 1640192506Syongari cmdsts = le32toh(cur_tx->nge_cmdsts); 1641192506Syongari if ((cmdsts & NGE_CMDSTS_OWN) != 0) 164276479Swpaul break; 1643192506Syongari sc->nge_cdata.nge_tx_cnt--; 1644192506Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1645192506Syongari if ((cmdsts & NGE_CMDSTS_MORE) != 0) 164676479Swpaul continue; 164776479Swpaul 1648192506Syongari txd = &sc->nge_cdata.nge_txdesc[cons]; 1649192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap, 1650192506Syongari BUS_DMASYNC_POSTWRITE); 1651192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap); 1652192506Syongari if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1653271812Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1654192506Syongari if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0) 1655271812Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1656192506Syongari if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0) 1657271812Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1658192506Syongari } else 1659271812Sglebius if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 166076479Swpaul 1661271812Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (cmdsts & NGE_TXSTAT_COLLCNT) >> 16); 1662192506Syongari KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1663192506Syongari __func__)); 1664192506Syongari m_freem(txd->tx_m); 1665192506Syongari txd->tx_m = NULL; 166676479Swpaul } 166776479Swpaul 1668192506Syongari sc->nge_cdata.nge_tx_cons = cons; 1669192506Syongari if (sc->nge_cdata.nge_tx_cnt == 0) 1670192506Syongari sc->nge_watchdog_timer = 0; 167176479Swpaul} 167276479Swpaul 167399497Salfredstatic void 1674192288Syongaringe_tick(void *xsc) 167576479Swpaul{ 1676192297Syongari struct nge_softc *sc; 1677192297Syongari struct mii_data *mii; 167876479Swpaul 1679151296Sjhb sc = xsc; 1680135250Swpaul NGE_LOCK_ASSERT(sc); 1681192506Syongari mii = device_get_softc(sc->nge_miibus); 1682192506Syongari mii_tick(mii); 1683192506Syongari /* 1684192506Syongari * For PHYs that does not reset established link, it is 1685192506Syongari * necessary to check whether driver still have a valid 1686192506Syongari * link(e.g link state change callback is not called). 1687192506Syongari * Otherwise, driver think it lost link because driver 1688192506Syongari * initialization routine clears link state flag. 1689192506Syongari */ 1690192506Syongari if ((sc->nge_flags & NGE_FLAG_LINK) == 0) 1691192506Syongari nge_miibus_statchg(sc->nge_dev); 1692192506Syongari nge_stats_update(sc); 1693192506Syongari nge_watchdog(sc); 1694192506Syongari callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1695192506Syongari} 1696192506Syongari 1697192506Syongaristatic void 1698192506Syongaringe_stats_update(struct nge_softc *sc) 1699192506Syongari{ 1700192506Syongari struct ifnet *ifp; 1701192506Syongari struct nge_stats now, *stats, *nstats; 1702192506Syongari 1703192506Syongari NGE_LOCK_ASSERT(sc); 1704192506Syongari 1705147256Sbrooks ifp = sc->nge_ifp; 1706192506Syongari stats = &now; 1707192506Syongari stats->rx_pkts_errs = 1708192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF; 1709192506Syongari stats->rx_crc_errs = 1710192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF; 1711192506Syongari stats->rx_fifo_oflows = 1712192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF; 1713192506Syongari stats->rx_align_errs = 1714192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF; 1715192506Syongari stats->rx_sym_errs = 1716192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF; 1717192506Syongari stats->rx_pkts_jumbos = 1718192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF; 1719192506Syongari stats->rx_len_errs = 1720192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF; 1721192506Syongari stats->rx_unctl_frames = 1722192506Syongari CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF; 1723192506Syongari stats->rx_pause = 1724192506Syongari CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF; 1725192506Syongari stats->tx_pause = 1726192506Syongari CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF; 1727192506Syongari stats->tx_seq_errs = 1728192506Syongari CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF; 172976479Swpaul 1730192506Syongari /* 1731192506Syongari * Since we've accept errored frames exclude Rx length errors. 1732192506Syongari */ 1733271812Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 1734271812Sglebius stats->rx_pkts_errs + stats->rx_crc_errs + 1735271812Sglebius stats->rx_fifo_oflows + stats->rx_sym_errs); 1736101540Sambrisko 1737192506Syongari nstats = &sc->nge_stats; 1738192506Syongari nstats->rx_pkts_errs += stats->rx_pkts_errs; 1739192506Syongari nstats->rx_crc_errs += stats->rx_crc_errs; 1740192506Syongari nstats->rx_fifo_oflows += stats->rx_fifo_oflows; 1741192506Syongari nstats->rx_align_errs += stats->rx_align_errs; 1742192506Syongari nstats->rx_sym_errs += stats->rx_sym_errs; 1743192506Syongari nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos; 1744192506Syongari nstats->rx_len_errs += stats->rx_len_errs; 1745192506Syongari nstats->rx_unctl_frames += stats->rx_unctl_frames; 1746192506Syongari nstats->rx_pause += stats->rx_pause; 1747192506Syongari nstats->tx_pause += stats->tx_pause; 1748192506Syongari nstats->tx_seq_errs += stats->tx_seq_errs; 174976479Swpaul} 175076479Swpaul 1751106507Ssimokawa#ifdef DEVICE_POLLING 1752106507Ssimokawastatic poll_handler_t nge_poll; 1753106507Ssimokawa 1754193105Sattiliostatic int 1755106507Ssimokawange_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1756106507Ssimokawa{ 1757192506Syongari struct nge_softc *sc; 1758193105Sattilio int rx_npkts = 0; 1759106507Ssimokawa 1760192506Syongari sc = ifp->if_softc; 1761192506Syongari 1762135250Swpaul NGE_LOCK(sc); 1763192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1764135250Swpaul NGE_UNLOCK(sc); 1765193105Sattilio return (rx_npkts); 1766106507Ssimokawa } 1767106507Ssimokawa 1768106507Ssimokawa /* 1769106507Ssimokawa * On the nge, reading the status register also clears it. 1770106507Ssimokawa * So before returning to intr mode we must make sure that all 1771106507Ssimokawa * possible pending sources of interrupts have been served. 1772106507Ssimokawa * In practice this means run to completion the *eof routines, 1773192506Syongari * and then call the interrupt routine. 1774106507Ssimokawa */ 1775106507Ssimokawa sc->rxcycles = count; 1776193105Sattilio rx_npkts = nge_rxeof(sc); 1777106507Ssimokawa nge_txeof(sc); 1778192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1779135250Swpaul nge_start_locked(ifp); 1780106507Ssimokawa 1781106507Ssimokawa if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1782192294Syongari uint32_t status; 1783106507Ssimokawa 1784106507Ssimokawa /* Reading the ISR register clears all interrupts. */ 1785106507Ssimokawa status = CSR_READ_4(sc, NGE_ISR); 1786106507Ssimokawa 1787192506Syongari if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0) 1788193105Sattilio rx_npkts += nge_rxeof(sc); 1789106507Ssimokawa 1790192506Syongari if ((status & NGE_ISR_RX_IDLE) != 0) 1791106507Ssimokawa NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1792106507Ssimokawa 1793192506Syongari if ((status & NGE_ISR_SYSERR) != 0) { 1794192506Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1795135250Swpaul nge_init_locked(sc); 1796106507Ssimokawa } 1797106507Ssimokawa } 1798135250Swpaul NGE_UNLOCK(sc); 1799193105Sattilio return (rx_npkts); 1800106507Ssimokawa} 1801106507Ssimokawa#endif /* DEVICE_POLLING */ 1802106507Ssimokawa 1803106507Ssimokawastatic void 1804192288Syongaringe_intr(void *arg) 180576479Swpaul{ 1806192297Syongari struct nge_softc *sc; 1807192297Syongari struct ifnet *ifp; 1808192297Syongari uint32_t status; 180976479Swpaul 1810192506Syongari sc = (struct nge_softc *)arg; 1811147256Sbrooks ifp = sc->nge_ifp; 181276479Swpaul 1813135250Swpaul NGE_LOCK(sc); 1814192506Syongari 1815192506Syongari if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0) 1816192506Syongari goto done_locked; 1817192506Syongari 1818192506Syongari /* Reading the ISR register clears all interrupts. */ 1819192506Syongari status = CSR_READ_4(sc, NGE_ISR); 1820192506Syongari if (status == 0xffffffff || (status & NGE_INTRS) == 0) 1821192506Syongari goto done_locked; 1822106507Ssimokawa#ifdef DEVICE_POLLING 1823192506Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1824192506Syongari goto done_locked; 1825150789Sglebius#endif 1826192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1827192506Syongari goto done_locked; 1828106507Ssimokawa 182976479Swpaul /* Disable interrupts. */ 183076479Swpaul CSR_WRITE_4(sc, NGE_IER, 0); 183176479Swpaul 1832101540Sambrisko /* Data LED on for TBI mode */ 1833192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1834192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 1835192506Syongari CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT); 1836101540Sambrisko 1837192506Syongari for (; (status & NGE_INTRS) != 0;) { 1838192506Syongari if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR | 1839192506Syongari NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0) 184076479Swpaul nge_txeof(sc); 184176479Swpaul 1842192506Syongari if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR | 1843192506Syongari NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW | 1844192506Syongari NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0) 184576479Swpaul nge_rxeof(sc); 184694612Sphk 1847192506Syongari if ((status & NGE_ISR_RX_IDLE) != 0) 184894612Sphk NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 184994612Sphk 1850192506Syongari if ((status & NGE_ISR_SYSERR) != 0) { 1851148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1852135250Swpaul nge_init_locked(sc); 185376479Swpaul } 1854192506Syongari /* Reading the ISR register clears all interrupts. */ 1855192506Syongari status = CSR_READ_4(sc, NGE_ISR); 185676479Swpaul } 185776479Swpaul 185876479Swpaul /* Re-enable interrupts. */ 185976479Swpaul CSR_WRITE_4(sc, NGE_IER, 1); 186076479Swpaul 1861192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1862135250Swpaul nge_start_locked(ifp); 186376479Swpaul 1864101540Sambrisko /* Data LED off for TBI mode */ 1865192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1866192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 1867192506Syongari CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 1868101540Sambrisko 1869192506Syongaridone_locked: 1870135250Swpaul NGE_UNLOCK(sc); 187176479Swpaul} 187276479Swpaul 187376479Swpaul/* 187476479Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 187576479Swpaul * pointers to the fragment pointers. 187676479Swpaul */ 187799497Salfredstatic int 1878192506Syongaringe_encap(struct nge_softc *sc, struct mbuf **m_head) 187976479Swpaul{ 1880192506Syongari struct nge_txdesc *txd, *txd_last; 1881192506Syongari struct nge_desc *desc; 1882192297Syongari struct mbuf *m; 1883192506Syongari bus_dmamap_t map; 1884192506Syongari bus_dma_segment_t txsegs[NGE_MAXTXSEGS]; 1885192506Syongari int error, i, nsegs, prod, si; 188676479Swpaul 1887192506Syongari NGE_LOCK_ASSERT(sc); 188876479Swpaul 1889192506Syongari m = *m_head; 1890192506Syongari prod = sc->nge_cdata.nge_tx_prod; 1891192506Syongari txd = &sc->nge_cdata.nge_txdesc[prod]; 1892192506Syongari txd_last = txd; 1893192506Syongari map = txd->tx_dmamap; 1894192506Syongari error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map, 1895192506Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1896192506Syongari if (error == EFBIG) { 1897243857Sglebius m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS); 1898192506Syongari if (m == NULL) { 1899192506Syongari m_freem(*m_head); 1900192506Syongari *m_head = NULL; 1901192506Syongari return (ENOBUFS); 190276479Swpaul } 1903192506Syongari *m_head = m; 1904192506Syongari error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, 1905192506Syongari map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1906192506Syongari if (error != 0) { 1907192506Syongari m_freem(*m_head); 1908192506Syongari *m_head = NULL; 1909192506Syongari return (error); 1910192506Syongari } 1911192506Syongari } else if (error != 0) 1912192506Syongari return (error); 1913192506Syongari if (nsegs == 0) { 1914192506Syongari m_freem(*m_head); 1915192506Syongari *m_head = NULL; 1916192506Syongari return (EIO); 191776479Swpaul } 191876479Swpaul 1919192506Syongari /* Check number of available descriptors. */ 1920192506Syongari if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) { 1921192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map); 1922192292Syongari return (ENOBUFS); 1923192506Syongari } 192476479Swpaul 1925192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE); 1926192506Syongari 1927192506Syongari si = prod; 1928192506Syongari for (i = 0; i < nsegs; i++) { 1929192506Syongari desc = &sc->nge_rdata.nge_tx_ring[prod]; 1930192506Syongari desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr)); 1931192506Syongari if (i == 0) 1932192506Syongari desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1933192506Syongari NGE_CMDSTS_MORE); 1934192506Syongari else 1935192506Syongari desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1936192506Syongari NGE_CMDSTS_MORE | NGE_CMDSTS_OWN); 1937192506Syongari desc->nge_extsts = 0; 1938192506Syongari sc->nge_cdata.nge_tx_cnt++; 1939192506Syongari NGE_INC(prod, NGE_TX_RING_CNT); 194076479Swpaul } 1941192506Syongari /* Update producer index. */ 1942192506Syongari sc->nge_cdata.nge_tx_prod = prod; 194376479Swpaul 1944192506Syongari prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT; 1945192506Syongari desc = &sc->nge_rdata.nge_tx_ring[prod]; 1946192506Syongari /* Check if we have a VLAN tag to insert. */ 1947192506Syongari if ((m->m_flags & M_VLANTAG) != 0) 1948192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT | 1949192506Syongari bswap16(m->m_pkthdr.ether_vtag)); 1950192506Syongari /* Set EOP on the last desciptor. */ 1951192506Syongari desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE); 1952192506Syongari 1953192506Syongari /* Set checksum offload in the first descriptor. */ 1954192506Syongari desc = &sc->nge_rdata.nge_tx_ring[si]; 1955192506Syongari if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) { 1956192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1957192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM); 1958192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1959192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM); 1960192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1961192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM); 196276479Swpaul } 1963192506Syongari /* Lastly, turn the first descriptor ownership to hardware. */ 1964192506Syongari desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN); 196576479Swpaul 1966192506Syongari txd = &sc->nge_cdata.nge_txdesc[prod]; 1967192506Syongari map = txd_last->tx_dmamap; 1968192506Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1969192506Syongari txd->tx_dmamap = map; 1970192506Syongari txd->tx_m = m; 197176479Swpaul 1972192292Syongari return (0); 197376479Swpaul} 197476479Swpaul 197576479Swpaul/* 197676479Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 197776479Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 197876479Swpaul * copy of the pointers since the transmit list fragment pointers are 197976479Swpaul * physical addresses. 198076479Swpaul */ 198176479Swpaul 198299497Salfredstatic void 1983192288Syongaringe_start(struct ifnet *ifp) 198476479Swpaul{ 1985192297Syongari struct nge_softc *sc; 1986135250Swpaul 1987135250Swpaul sc = ifp->if_softc; 1988135250Swpaul NGE_LOCK(sc); 1989135250Swpaul nge_start_locked(ifp); 1990135250Swpaul NGE_UNLOCK(sc); 1991135250Swpaul} 1992135250Swpaul 1993135250Swpaulstatic void 1994192288Syongaringe_start_locked(struct ifnet *ifp) 1995135250Swpaul{ 1996192297Syongari struct nge_softc *sc; 1997192506Syongari struct mbuf *m_head; 1998192506Syongari int enq; 199976479Swpaul 200076479Swpaul sc = ifp->if_softc; 200176479Swpaul 2002192506Syongari NGE_LOCK_ASSERT(sc); 200376479Swpaul 2004192506Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2005192506Syongari IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0) 200676479Swpaul return; 200776479Swpaul 2008192506Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2009192506Syongari sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) { 2010192506Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 201176479Swpaul if (m_head == NULL) 201276479Swpaul break; 2013192506Syongari /* 2014192506Syongari * Pack the data into the transmit ring. If we 2015192506Syongari * don't have room, set the OACTIVE flag and wait 2016192506Syongari * for the NIC to drain the ring. 2017192506Syongari */ 2018192506Syongari if (nge_encap(sc, &m_head)) { 2019192506Syongari if (m_head == NULL) 2020192506Syongari break; 2021192506Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2022148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 202376479Swpaul break; 202476479Swpaul } 202576479Swpaul 2026192506Syongari enq++; 202776479Swpaul /* 202876479Swpaul * If there's a BPF listener, bounce a copy of this frame 202976479Swpaul * to him. 203076479Swpaul */ 2031167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 203276479Swpaul } 203376479Swpaul 2034192506Syongari if (enq > 0) { 2035192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 2036192506Syongari sc->nge_cdata.nge_tx_ring_map, 2037192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2038192506Syongari /* Transmit */ 2039192506Syongari NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 204076479Swpaul 2041192506Syongari /* Set a timeout in case the chip goes out to lunch. */ 2042192506Syongari sc->nge_watchdog_timer = 5; 2043192506Syongari } 204476479Swpaul} 204576479Swpaul 204699497Salfredstatic void 2047192288Syongaringe_init(void *xsc) 204876479Swpaul{ 2049192297Syongari struct nge_softc *sc = xsc; 2050135250Swpaul 2051135250Swpaul NGE_LOCK(sc); 2052135250Swpaul nge_init_locked(sc); 2053135250Swpaul NGE_UNLOCK(sc); 2054135250Swpaul} 2055135250Swpaul 2056135250Swpaulstatic void 2057192288Syongaringe_init_locked(struct nge_softc *sc) 2058135250Swpaul{ 2059192297Syongari struct ifnet *ifp = sc->nge_ifp; 2060192297Syongari struct mii_data *mii; 2061192506Syongari uint8_t *eaddr; 2062192506Syongari uint32_t reg; 206376479Swpaul 2064135250Swpaul NGE_LOCK_ASSERT(sc); 2065135250Swpaul 2066192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 206776479Swpaul return; 206876479Swpaul 206976479Swpaul /* 207076479Swpaul * Cancel pending I/O and free all RX/TX buffers. 207176479Swpaul */ 207276479Swpaul nge_stop(sc); 207376479Swpaul 2074192506Syongari /* Reset the adapter. */ 2075192506Syongari nge_reset(sc); 207676479Swpaul 2077192506Syongari /* Disable Rx filter prior to programming Rx filter. */ 2078192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0); 2079226995Smarius CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 2080192506Syongari 2081192506Syongari mii = device_get_softc(sc->nge_miibus); 2082192506Syongari 2083192506Syongari /* Set MAC address. */ 2084192506Syongari eaddr = IF_LLADDR(sc->nge_ifp); 208576479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 2086192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]); 208776479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 2088192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]); 208976479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 2090192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]); 209176479Swpaul 209276479Swpaul /* Init circular RX list. */ 209376479Swpaul if (nge_list_rx_init(sc) == ENOBUFS) { 2094162321Sglebius device_printf(sc->nge_dev, "initialization failed: no " 2095151296Sjhb "memory for rx buffers\n"); 209676479Swpaul nge_stop(sc); 209776479Swpaul return; 209876479Swpaul } 209976479Swpaul 210076479Swpaul /* 210176479Swpaul * Init tx descriptors. 210276479Swpaul */ 210376479Swpaul nge_list_tx_init(sc); 210476479Swpaul 2105192506Syongari /* Set Rx filter. */ 2106192506Syongari nge_rxfilter(sc); 2107192506Syongari 2108192506Syongari /* Disable PRIQ ctl. */ 2109192506Syongari CSR_WRITE_4(sc, NGE_PRIOQCTL, 0); 2110192506Syongari 211176479Swpaul /* 2112298955Spfg * Set pause frames parameters. 2113192506Syongari * Rx stat FIFO hi-threshold : 2 or more packets 2114192506Syongari * Rx stat FIFO lo-threshold : less than 2 packets 2115192506Syongari * Rx data FIFO hi-threshold : 2K or more bytes 2116192506Syongari * Rx data FIFO lo-threshold : less than 2K bytes 2117192506Syongari * pause time : (512ns * 0xffff) -> 33.55ms 211876479Swpaul */ 2119192506Syongari CSR_WRITE_4(sc, NGE_PAUSECSR, 2120192506Syongari NGE_PAUSECSR_PAUSE_ON_MCAST | 2121192506Syongari NGE_PAUSECSR_PAUSE_ON_DA | 2122192506Syongari ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) | 2123192506Syongari ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) | 2124192506Syongari ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) | 2125192506Syongari ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) | 2126192506Syongari NGE_PAUSECSR_CNT); 212776479Swpaul 212876479Swpaul /* 212976479Swpaul * Load the address of the RX and TX lists. 213076479Swpaul */ 2131192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 2132192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 2133192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 2134192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 2135192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 2136192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 2137192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 2138192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 213976479Swpaul 2140192506Syongari /* Set RX configuration. */ 214176479Swpaul CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 2142192506Syongari 2143192506Syongari CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0); 214476479Swpaul /* 214576479Swpaul * Enable hardware checksum validation for all IPv4 214676479Swpaul * packets, do not reject packets with bad checksums. 214776479Swpaul */ 2148192506Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2149192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 215076479Swpaul 215176479Swpaul /* 215283115Sbrooks * Tell the chip to detect and strip VLAN tag info from 215383115Sbrooks * received frames. The tag will be provided in the extsts 215483115Sbrooks * field in the RX descriptors. 215576479Swpaul */ 2156192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB); 2157192506Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2158192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB); 215976479Swpaul 2160192506Syongari /* Set TX configuration. */ 216176479Swpaul CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 216276479Swpaul 216376479Swpaul /* 216476479Swpaul * Enable TX IPv4 checksumming on a per-packet basis. 216576479Swpaul */ 216678323Swpaul CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 216776479Swpaul 216876479Swpaul /* 216983115Sbrooks * Tell the chip to insert VLAN tags on a per-packet basis as 217083115Sbrooks * dictated by the code in the frame encapsulation routine. 217176479Swpaul */ 217276479Swpaul NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 217376479Swpaul 217476479Swpaul /* 217576479Swpaul * Enable the delivery of PHY interrupts based on 217677842Swpaul * link/speed/duplex status changes. Also enable the 217777842Swpaul * extsts field in the DMA descriptors (needed for 217877842Swpaul * TCP/IP checksum offload on transmit). 217976479Swpaul */ 2180192506Syongari NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 2181192506Syongari NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 218276479Swpaul 218376479Swpaul /* 218479562Swpaul * Configure interrupt holdoff (moderation). We can 218579562Swpaul * have the chip delay interrupt delivery for a certain 218679562Swpaul * period. Units are in 100us, and the max setting 218779562Swpaul * is 25500us (0xFF x 100us). Default is a 100us holdoff. 218879562Swpaul */ 2189192506Syongari CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff); 219079562Swpaul 219179562Swpaul /* 2192192506Syongari * Enable MAC statistics counters and clear. 2193192506Syongari */ 2194192506Syongari reg = CSR_READ_4(sc, NGE_MIBCTL); 2195192506Syongari reg &= ~NGE_MIBCTL_FREEZE_CNT; 2196192506Syongari reg |= NGE_MIBCTL_CLEAR_CNT; 2197192506Syongari CSR_WRITE_4(sc, NGE_MIBCTL, reg); 2198192506Syongari 2199192506Syongari /* 220076479Swpaul * Enable interrupts. 220176479Swpaul */ 220276479Swpaul CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2203106507Ssimokawa#ifdef DEVICE_POLLING 2204106507Ssimokawa /* 2205106507Ssimokawa * ... only enable interrupts if we are not polling, make sure 2206106507Ssimokawa * they are off otherwise. 2207106507Ssimokawa */ 2208192506Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2209106507Ssimokawa CSR_WRITE_4(sc, NGE_IER, 0); 2210106507Ssimokawa else 2211150789Sglebius#endif 221276479Swpaul CSR_WRITE_4(sc, NGE_IER, 1); 221376479Swpaul 2214192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 2215192506Syongari mii_mediachg(mii); 221676479Swpaul 2217192506Syongari sc->nge_watchdog_timer = 0; 2218192506Syongari callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 221976479Swpaul 2220148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2221148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 222276479Swpaul} 222376479Swpaul 222476479Swpaul/* 222576479Swpaul * Set media options. 222676479Swpaul */ 222799497Salfredstatic int 2228192506Syongaringe_mediachange(struct ifnet *ifp) 222976479Swpaul{ 2230192297Syongari struct nge_softc *sc; 2231192506Syongari struct mii_data *mii; 2232192506Syongari struct mii_softc *miisc; 2233192506Syongari int error; 2234151296Sjhb 2235151296Sjhb sc = ifp->if_softc; 2236151296Sjhb NGE_LOCK(sc); 2237192506Syongari mii = device_get_softc(sc->nge_miibus); 2238221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2239221407Smarius PHY_RESET(miisc); 2240192506Syongari error = mii_mediachg(mii); 2241151296Sjhb NGE_UNLOCK(sc); 2242151296Sjhb 2243192506Syongari return (error); 224476479Swpaul} 224576479Swpaul 224676479Swpaul/* 224776479Swpaul * Report current media status. 224876479Swpaul */ 224999497Salfredstatic void 2250192506Syongaringe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 225176479Swpaul{ 2252192297Syongari struct nge_softc *sc; 2253192297Syongari struct mii_data *mii; 225476479Swpaul 225576479Swpaul sc = ifp->if_softc; 2256151296Sjhb NGE_LOCK(sc); 2257192506Syongari mii = device_get_softc(sc->nge_miibus); 2258192506Syongari mii_pollstat(mii); 2259192506Syongari ifmr->ifm_active = mii->mii_media_active; 2260192506Syongari ifmr->ifm_status = mii->mii_media_status; 2261226478Syongari NGE_UNLOCK(sc); 226276479Swpaul} 226376479Swpaul 226499497Salfredstatic int 2265192288Syongaringe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 226676479Swpaul{ 2267192297Syongari struct nge_softc *sc = ifp->if_softc; 2268192297Syongari struct ifreq *ifr = (struct ifreq *) data; 2269192297Syongari struct mii_data *mii; 2270192506Syongari int error = 0, mask; 227176479Swpaul 2272192292Syongari switch (command) { 227376479Swpaul case SIOCSIFMTU: 2274192506Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU) 227576479Swpaul error = EINVAL; 227678323Swpaul else { 2277151296Sjhb NGE_LOCK(sc); 227876479Swpaul ifp->if_mtu = ifr->ifr_mtu; 227978323Swpaul /* 228078323Swpaul * Workaround: if the MTU is larger than 228178323Swpaul * 8152 (TX FIFO size minus 64 minus 18), turn off 228278323Swpaul * TX checksum offloading. 228378323Swpaul */ 2284129632Syar if (ifr->ifr_mtu >= 8152) { 2285129632Syar ifp->if_capenable &= ~IFCAP_TXCSUM; 2286192506Syongari ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2287129632Syar } else { 2288129632Syar ifp->if_capenable |= IFCAP_TXCSUM; 2289192506Syongari ifp->if_hwassist |= NGE_CSUM_FEATURES; 2290129632Syar } 2291151296Sjhb NGE_UNLOCK(sc); 2292192506Syongari VLAN_CAPABILITIES(ifp); 229378323Swpaul } 229476479Swpaul break; 229576479Swpaul case SIOCSIFFLAGS: 2296135250Swpaul NGE_LOCK(sc); 2297192506Syongari if ((ifp->if_flags & IFF_UP) != 0) { 2298192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2299192506Syongari if ((ifp->if_flags ^ sc->nge_if_flags) & 2300192506Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2301192506Syongari nge_rxfilter(sc); 230276479Swpaul } else { 2303192506Syongari if ((sc->nge_flags & NGE_FLAG_DETACH) == 0) 2304192506Syongari nge_init_locked(sc); 230576479Swpaul } 230676479Swpaul } else { 2307192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 230876479Swpaul nge_stop(sc); 230976479Swpaul } 231076479Swpaul sc->nge_if_flags = ifp->if_flags; 2311135250Swpaul NGE_UNLOCK(sc); 231276479Swpaul error = 0; 231376479Swpaul break; 231476479Swpaul case SIOCADDMULTI: 231576479Swpaul case SIOCDELMULTI: 2316135250Swpaul NGE_LOCK(sc); 2317277050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2318277050Syongari nge_rxfilter(sc); 2319135250Swpaul NGE_UNLOCK(sc); 232076479Swpaul break; 232176479Swpaul case SIOCGIFMEDIA: 232276479Swpaul case SIOCSIFMEDIA: 2323192506Syongari mii = device_get_softc(sc->nge_miibus); 2324192506Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 232576479Swpaul break; 2326128132Sru case SIOCSIFCAP: 2327192506Syongari NGE_LOCK(sc); 2328192506Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2329150789Sglebius#ifdef DEVICE_POLLING 2330192506Syongari if ((mask & IFCAP_POLLING) != 0 && 2331192506Syongari (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2332192506Syongari ifp->if_capenable ^= IFCAP_POLLING; 2333192506Syongari if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2334192506Syongari error = ether_poll_register(nge_poll, ifp); 2335192506Syongari if (error != 0) { 2336192506Syongari NGE_UNLOCK(sc); 2337192506Syongari break; 2338192506Syongari } 2339192506Syongari /* Disable interrupts. */ 2340192506Syongari CSR_WRITE_4(sc, NGE_IER, 0); 2341192506Syongari } else { 2342192506Syongari error = ether_poll_deregister(ifp); 2343192506Syongari /* Enable interrupts. */ 2344192506Syongari CSR_WRITE_4(sc, NGE_IER, 1); 2345192506Syongari } 2346192506Syongari } 2347192506Syongari#endif /* DEVICE_POLLING */ 2348192506Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2349192506Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2350192506Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2351192506Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2352192506Syongari ifp->if_hwassist |= NGE_CSUM_FEATURES; 2353192506Syongari else 2354192506Syongari ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2355192506Syongari } 2356192506Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2357192506Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2358192506Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2359192290Syongari 2360192506Syongari if ((mask & IFCAP_WOL) != 0 && 2361192506Syongari (ifp->if_capabilities & IFCAP_WOL) != 0) { 2362192506Syongari if ((mask & IFCAP_WOL_UCAST) != 0) 2363192506Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2364192506Syongari if ((mask & IFCAP_WOL_MCAST) != 0) 2365192506Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 2366192506Syongari if ((mask & IFCAP_WOL_MAGIC) != 0) 2367192506Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2368150789Sglebius } 2369192506Syongari 2370192506Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2371192506Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2372192506Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2373192506Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2374192506Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2375192506Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2376192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2377192506Syongari if ((ifp->if_capenable & 2378192506Syongari IFCAP_VLAN_HWTAGGING) != 0) 2379192506Syongari NGE_SETBIT(sc, 2380192506Syongari NGE_VLAN_IP_RXCTL, 2381192506Syongari NGE_VIPRXCTL_TAG_STRIP_ENB); 2382192506Syongari else 2383192506Syongari NGE_CLRBIT(sc, 2384192506Syongari NGE_VLAN_IP_RXCTL, 2385192506Syongari NGE_VIPRXCTL_TAG_STRIP_ENB); 2386192506Syongari } 2387150789Sglebius } 2388192506Syongari /* 2389192506Syongari * Both VLAN hardware tagging and checksum offload is 2390192506Syongari * required to do checksum offload on VLAN interface. 2391192506Syongari */ 2392192506Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2393192506Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2394192506Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2395192506Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2396192506Syongari NGE_UNLOCK(sc); 2397192506Syongari VLAN_CAPABILITIES(ifp); 2398128132Sru break; 239976479Swpaul default: 2400106937Ssam error = ether_ioctl(ifp, command, data); 240176479Swpaul break; 240276479Swpaul } 240376479Swpaul 2404192292Syongari return (error); 240576479Swpaul} 240676479Swpaul 240799497Salfredstatic void 2408192506Syongaringe_watchdog(struct nge_softc *sc) 240976479Swpaul{ 2410192506Syongari struct ifnet *ifp; 241176479Swpaul 2412192506Syongari NGE_LOCK_ASSERT(sc); 241376479Swpaul 2414192506Syongari if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer) 2415192506Syongari return; 2416192506Syongari 2417192506Syongari ifp = sc->nge_ifp; 2418271812Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2419162321Sglebius if_printf(ifp, "watchdog timeout\n"); 242076479Swpaul 2421148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2422135250Swpaul nge_init_locked(sc); 242376479Swpaul 2424192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2425135250Swpaul nge_start_locked(ifp); 2426192506Syongari} 242776479Swpaul 2428192506Syongaristatic int 2429192506Syongaringe_stop_mac(struct nge_softc *sc) 2430192506Syongari{ 2431192506Syongari uint32_t reg; 2432192506Syongari int i; 2433192506Syongari 2434192506Syongari NGE_LOCK_ASSERT(sc); 2435192506Syongari 2436192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 2437192506Syongari if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) { 2438192506Syongari reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE); 2439192506Syongari reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE; 2440192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 2441192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 2442192506Syongari DELAY(1); 2443192506Syongari if ((CSR_READ_4(sc, NGE_CSR) & 2444192506Syongari (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0) 2445192506Syongari break; 2446192506Syongari } 2447192506Syongari if (i == NGE_TIMEOUT) 2448192506Syongari return (ETIMEDOUT); 2449192506Syongari } 2450192506Syongari 2451192506Syongari return (0); 245276479Swpaul} 245376479Swpaul 245476479Swpaul/* 245576479Swpaul * Stop the adapter and free any mbufs allocated to the 245676479Swpaul * RX and TX lists. 245776479Swpaul */ 245899497Salfredstatic void 2459192288Syongaringe_stop(struct nge_softc *sc) 246076479Swpaul{ 2461192506Syongari struct nge_txdesc *txd; 2462192506Syongari struct nge_rxdesc *rxd; 2463192297Syongari int i; 2464192297Syongari struct ifnet *ifp; 246576479Swpaul 2466135250Swpaul NGE_LOCK_ASSERT(sc); 2467147256Sbrooks ifp = sc->nge_ifp; 246876479Swpaul 2469192506Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2470192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 2471135250Swpaul callout_stop(&sc->nge_stat_ch); 2472192506Syongari sc->nge_watchdog_timer = 0; 2473192506Syongari 247476479Swpaul CSR_WRITE_4(sc, NGE_IER, 0); 247576479Swpaul CSR_WRITE_4(sc, NGE_IMR, 0); 2476192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 2477192506Syongari device_printf(sc->nge_dev, 2478192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 2479192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0); 2480192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0); 2481192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2482192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2483192506Syongari nge_stats_update(sc); 2484192506Syongari if (sc->nge_head != NULL) { 2485192506Syongari m_freem(sc->nge_head); 2486192506Syongari sc->nge_head = sc->nge_tail = NULL; 2487192506Syongari } 248876479Swpaul 248976479Swpaul /* 2490192506Syongari * Free RX and TX mbufs still in the queues. 249176479Swpaul */ 2492192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 2493192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 2494192506Syongari if (rxd->rx_m != NULL) { 2495192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, 2496192506Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2497192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, 2498192506Syongari rxd->rx_dmamap); 2499192506Syongari m_freem(rxd->rx_m); 2500192506Syongari rxd->rx_m = NULL; 250176479Swpaul } 250276479Swpaul } 2503192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 2504192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 2505192506Syongari if (txd->tx_m != NULL) { 2506192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 2507192506Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2508192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 2509192506Syongari txd->tx_dmamap); 2510192506Syongari m_freem(txd->tx_m); 2511192506Syongari txd->tx_m = NULL; 251276479Swpaul } 251376479Swpaul } 2514192506Syongari} 251576479Swpaul 2516192506Syongari/* 2517192506Syongari * Before setting WOL bits, caller should have stopped Receiver. 2518192506Syongari */ 2519192506Syongaristatic void 2520192506Syongaringe_wol(struct nge_softc *sc) 2521192506Syongari{ 2522192506Syongari struct ifnet *ifp; 2523192506Syongari uint32_t reg; 2524192506Syongari uint16_t pmstat; 2525192506Syongari int pmc; 252676479Swpaul 2527192506Syongari NGE_LOCK_ASSERT(sc); 2528192506Syongari 2529219902Sjhb if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0) 2530192506Syongari return; 2531192506Syongari 2532192506Syongari ifp = sc->nge_ifp; 2533192506Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2534192506Syongari /* Disable WOL & disconnect CLKRUN to save power. */ 2535192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, 0); 2536192506Syongari CSR_WRITE_4(sc, NGE_CLKRUN, 0); 2537192506Syongari } else { 2538192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 2539192506Syongari device_printf(sc->nge_dev, 2540192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 2541192506Syongari /* 2542192506Syongari * Make sure wake frames will be buffered in the Rx FIFO. 2543192506Syongari * (i.e. Silent Rx mode.) 2544192506Syongari */ 2545192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2546226995Smarius CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE); 2547192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2548226995Smarius CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE); 2549192506Syongari /* Enable Rx again. */ 2550192506Syongari NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2551226995Smarius CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE); 2552192506Syongari 2553192506Syongari /* Configure WOL events. */ 2554192506Syongari reg = 0; 2555192506Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2556192506Syongari reg |= NGE_WOLCSR_WAKE_ON_UNICAST; 2557192506Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2558192506Syongari reg |= NGE_WOLCSR_WAKE_ON_MULTICAST; 2559192506Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2560192506Syongari reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT; 2561192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, reg); 2562192506Syongari 2563192506Syongari /* Activate CLKRUN. */ 2564192506Syongari reg = CSR_READ_4(sc, NGE_CLKRUN); 2565192506Syongari reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB; 2566192506Syongari CSR_WRITE_4(sc, NGE_CLKRUN, reg); 2567192506Syongari } 2568192506Syongari 2569192506Syongari /* Request PME. */ 2570192506Syongari pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); 2571192506Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2572192506Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2573192506Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2574192506Syongari pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 257576479Swpaul} 257676479Swpaul 257776479Swpaul/* 257876479Swpaul * Stop all chip I/O so that the kernel's probe routines don't 257976479Swpaul * get confused by errant DMAs when rebooting. 258076479Swpaul */ 2581173839Syongaristatic int 2582192288Syongaringe_shutdown(device_t dev) 258376479Swpaul{ 2584192506Syongari 2585192506Syongari return (nge_suspend(dev)); 2586192506Syongari} 2587192506Syongari 2588192506Syongaristatic int 2589192506Syongaringe_suspend(device_t dev) 2590192506Syongari{ 2591192297Syongari struct nge_softc *sc; 259276479Swpaul 259376479Swpaul sc = device_get_softc(dev); 259476479Swpaul 2595135250Swpaul NGE_LOCK(sc); 259676479Swpaul nge_stop(sc); 2597192506Syongari nge_wol(sc); 2598192506Syongari sc->nge_flags |= NGE_FLAG_SUSPENDED; 2599135250Swpaul NGE_UNLOCK(sc); 260076479Swpaul 2601173839Syongari return (0); 260276479Swpaul} 2603192506Syongari 2604192506Syongaristatic int 2605192506Syongaringe_resume(device_t dev) 2606192506Syongari{ 2607192506Syongari struct nge_softc *sc; 2608192506Syongari struct ifnet *ifp; 2609192506Syongari uint16_t pmstat; 2610192506Syongari int pmc; 2611192506Syongari 2612192506Syongari sc = device_get_softc(dev); 2613192506Syongari 2614192506Syongari NGE_LOCK(sc); 2615192506Syongari ifp = sc->nge_ifp; 2616219902Sjhb if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { 2617192506Syongari /* Disable PME and clear PME status. */ 2618192506Syongari pmstat = pci_read_config(sc->nge_dev, 2619192506Syongari pmc + PCIR_POWER_STATUS, 2); 2620192506Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2621192506Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 2622192506Syongari pci_write_config(sc->nge_dev, 2623192506Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 2624192506Syongari } 2625192506Syongari } 2626192506Syongari if (ifp->if_flags & IFF_UP) { 2627192506Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2628192506Syongari nge_init_locked(sc); 2629192506Syongari } 2630192506Syongari 2631192506Syongari sc->nge_flags &= ~NGE_FLAG_SUSPENDED; 2632192506Syongari NGE_UNLOCK(sc); 2633192506Syongari 2634192506Syongari return (0); 2635192506Syongari} 2636192506Syongari 2637192506Syongari#define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2638192506Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2639192506Syongari 2640192506Syongaristatic void 2641192506Syongaringe_sysctl_node(struct nge_softc *sc) 2642192506Syongari{ 2643192506Syongari struct sysctl_ctx_list *ctx; 2644192506Syongari struct sysctl_oid_list *child, *parent; 2645192506Syongari struct sysctl_oid *tree; 2646192506Syongari struct nge_stats *stats; 2647192506Syongari int error; 2648192506Syongari 2649192506Syongari ctx = device_get_sysctl_ctx(sc->nge_dev); 2650192506Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev)); 2651192506Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", 2652192506Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->nge_int_holdoff, 0, 2653192506Syongari sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation"); 2654192506Syongari /* Pull in device tunables. */ 2655192506Syongari sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2656192506Syongari error = resource_int_value(device_get_name(sc->nge_dev), 2657192506Syongari device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff); 2658192506Syongari if (error == 0) { 2659192506Syongari if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN || 2660192506Syongari sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) { 2661192506Syongari device_printf(sc->nge_dev, 2662192506Syongari "int_holdoff value out of range; " 2663192506Syongari "using default: %d(%d us)\n", 2664192506Syongari NGE_INT_HOLDOFF_DEFAULT, 2665192506Syongari NGE_INT_HOLDOFF_DEFAULT * 100); 2666192506Syongari sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2667192506Syongari } 2668192506Syongari } 2669192506Syongari 2670192506Syongari stats = &sc->nge_stats; 2671192506Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2672192506Syongari NULL, "NGE statistics"); 2673192506Syongari parent = SYSCTL_CHILDREN(tree); 2674192506Syongari 2675192506Syongari /* Rx statistics. */ 2676192506Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2677192506Syongari NULL, "Rx MAC statistics"); 2678192506Syongari child = SYSCTL_CHILDREN(tree); 2679192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs", 2680192506Syongari &stats->rx_pkts_errs, 2681192506Syongari "Packet errors including both wire errors and FIFO overruns"); 2682192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 2683192506Syongari &stats->rx_crc_errs, "CRC errors"); 2684192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2685192506Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 2686192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2687192506Syongari &stats->rx_align_errs, "Frame alignment errors"); 2688192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2689192506Syongari &stats->rx_sym_errs, "One or more symbol errors"); 2690192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos", 2691192506Syongari &stats->rx_pkts_jumbos, 2692192506Syongari "Packets received with length greater than 1518 bytes"); 2693192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2694192506Syongari &stats->rx_len_errs, "In Range Length errors"); 2695192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames", 2696192506Syongari &stats->rx_unctl_frames, "Control frames with unsupported opcode"); 2697192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2698192506Syongari &stats->rx_pause, "Pause frames"); 2699192506Syongari 2700192506Syongari /* Tx statistics. */ 2701192506Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2702192506Syongari NULL, "Tx MAC statistics"); 2703192506Syongari child = SYSCTL_CHILDREN(tree); 2704192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2705192506Syongari &stats->tx_pause, "Pause frames"); 2706192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs", 2707192506Syongari &stats->tx_seq_errs, 2708192506Syongari "Loss of collision heartbeat during transmission"); 2709192506Syongari} 2710192506Syongari 2711192506Syongari#undef NGE_SYSCTL_STAT_ADD32 2712192506Syongari 2713192506Syongaristatic int 2714192506Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2715192506Syongari{ 2716192506Syongari int error, value; 2717192506Syongari 2718192506Syongari if (arg1 == NULL) 2719192506Syongari return (EINVAL); 2720192506Syongari value = *(int *)arg1; 2721192506Syongari error = sysctl_handle_int(oidp, &value, 0, req); 2722192506Syongari if (error != 0 || req->newptr == NULL) 2723192506Syongari return (error); 2724192506Syongari if (value < low || value > high) 2725192506Syongari return (EINVAL); 2726192506Syongari *(int *)arg1 = value; 2727192506Syongari 2728192506Syongari return (0); 2729192506Syongari} 2730192506Syongari 2731192506Syongaristatic int 2732192506Syongarisysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS) 2733192506Syongari{ 2734192506Syongari 2735192506Syongari return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN, 2736192506Syongari NGE_INT_HOLDOFF_MAX)); 2737192506Syongari} 2738