Searched refs:BCS0 (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/gpu/drm/i915/
H A Di915_pci.c271 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
319 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
387 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
395 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
454 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
461 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
506 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
522 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
569 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
590 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BI
[all...]
H A Di915_drv.h654 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
H A Di915_gpu_error.c1313 case BCS0:
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c81 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
82 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
83 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
84 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
85 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
135 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
136 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
137 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
138 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
139 {BCS0, RING_EXC
[all...]
H A Dexeclist.c50 [BCS0] = BCS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c429 #define R_BCS BIT(BCS0)
619 [BCS0] = {
1052 if (s->engine->id == BCS0 &&
1157 [BCS0] = {
H A Dscheduler.c169 } else if (workload->engine->id == BCS0)
H A Dhandlers.c334 engine_mask |= BIT(BCS0);
2090 id = BCS0;
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h113 BCS0, enumerator in enum:intel_engine_id
122 #define _BCS(n) (BCS0 + (n))
427 struct intel_context *bind_context; /* pinned, only for BCS0 */
H A Dintel_engine_user.c166 [COPY_ENGINE_CLASS] = { BCS0, 1 },
H A Dintel_gt.c1040 struct intel_engine_cs *engine = gt->engine[BCS0];
1079 struct intel_engine_cs *engine = gt->engine[BCS0];
H A Dintel_engine_cs.c71 [BCS0] = {
403 [BCS0] = GEN11_GRDOM_BLT,
436 [BCS0] = GEN6_GRDOM_BLT,
1493 if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
1732 [BCS0] = MSG_IDLE_BCS,
H A Dintel_mocs.c624 [BCS0] = __GEN9_BCS0_MOCS0,
H A Dgen8_engine_cs.c173 case BCS0:
H A Dintel_ring_submission.c96 case BCS0:
H A Dintel_ggtt.c308 ce = gt->engine[BCS0]->bind_context;
H A Dintel_execlists_submission.c3507 [BCS0] = GEN8_BCS_IRQ_SHIFT,
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2476 [I915_EXEC_BLT] = BCS0,

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