| /linux-master/arch/arm/include/debug/ |
| H A D | vexpress.S | 26 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
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| /linux-master/arch/arm/mach-tegra/ |
| H A D | reset-handler.S | 156 # Tegra20 is a Cortex-A9 r1p1
172 # Tegra30 is a Cortex-A9 r2p9
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| /linux-master/arch/m68k/fpsp040/ |
| H A D | bindec.S | 56 | sign of ISCALE, used in A9. Fp1 contains
67 | A9. Scale X -> Y.
332 | of ISCALE, used in A9. Fp1 contains 10^^(abs(ISCALE)) using
360 | d2: x/0 or 24 for A9
396 movel #24,%d2 |put 24 in d2 for A9
450 | A9. Scale X -> Y.
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| /linux-master/arch/arm/kernel/ |
| H A D | head.S | 535 @ Cortex-A9 CPU is present but SMP operations fault.
539 teq r3, r4 @ Check for ARM Cortex-A9
540 retne lr @ Not ARM Cortex-A9,
546 teq r0, #0x0 @ '0' on actual UP A9 hardware
547 beq __fixup_smp_on_up @ So its an A9 UP
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| /linux-master/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g4.c | 1429 #define A9 172 macro
1430 SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
1431 SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC);
1432 SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2);
1433 PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0),
1434 SIG_EXPR_LIST_PTR(A9, RGMII2RXD0));
1462 FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
1463 FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E
[all...] |
| H A D | pinctrl-aspeed-g5.c | 967 #define A9 130 macro
968 SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
969 PIN_DECL_1(A9, GPIOQ2, SCL4);
975 FUNC_GROUP_DECL(I2C4, A9, B9);
1922 ASPEED_PINCTRL_PIN(A9),
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| /linux-master/arch/arm/mm/ |
| H A D | cache-v7.S | 108 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
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| H A D | proc-v7.S | 503 /* Cortex-A9 Errata */
504 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
604 @ Cortex-A9 - needs more registers preserved across suspend/resume
682 * ARM Ltd. Cortex A9 processor.
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| /linux-master/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 173 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 PINMUX_IPSR_GPSR(IP1_7_4, A9),
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| H A D | pfc-r8a77990.c | 101 #define GPSR1_9 F_(A9, IP4_3_0)
248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
731 PINMUX_IPSR_GPSR(IP4_3_0, A9),
5130 [18] = RCAR_GP_PIN(1, 9), /* A9 */
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| H A D | pfc-sh7734.c | 635 PINMUX_IPSR_GPSR(IP0_19_18, A9),
1382 GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
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| H A D | pfc-r8a77980.c | 207 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
508 PINMUX_IPSR_GPSR(IP1_7_4, A9),
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| H A D | pfc-r8a77951.c | 118 #define GPSR1_9 F_(A9, IP3_3_0)
280 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
804 PINMUX_IPSR_GPSR(IP3_3_0, A9),
5683 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5950 [21] = RCAR_GP_PIN(1, 9), /* A9 */
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| H A D | pfc-r8a77965.c | 123 #define GPSR1_9 F_(A9, IP3_3_0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
810 PINMUX_IPSR_GPSR(IP3_3_0, A9),
5879 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
6143 [21] = RCAR_GP_PIN(1, 9), /* A9 */
|
| H A D | pfc-r8a7796.c | 123 #define GPSR1_9 F_(A9, IP3_3_0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
808 PINMUX_IPSR_GPSR(IP3_3_0, A9),
5638 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5902 [21] = RCAR_GP_PIN(1, 9), /* A9 */
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| H A D | pfc-r8a73a4.c | 333 F1(A9), F2(MMCD1_6), IRQ(32),
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| H A D | pfc-sh7264.c | 1277 GPIO_FN(A9),
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| H A D | pfc-r8a7792.c | 382 PINMUX_SINGLE(A9),
2726 [25] = RCAR_GP_PIN(2, 25), /* A9 */
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| H A D | pfc-r8a779a0.c | 367 #define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
829 PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
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| H A D | pfc-r8a77470.c | 717 PINMUX_IPSR_GPSR(IP5_11_8, A9),
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| H A D | pfc-sh7269.c | 1715 GPIO_FN(A9),
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| H A D | pfc-sh7757.c | 1630 GPIO_FN(A9),
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| H A D | pfc-r8a7778.c | 577 PINMUX_IPSR_GPSR(IP0_20, A9),
2887 [ 9] = RCAR_GP_PIN(0, 15), /* A9 */
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| H A D | pfc-r8a7791.c | 879 PINMUX_IPSR_GPSR(IP1_5_4, A9),
6601 [31] = RCAR_GP_PIN(0, 25), /* A9 */
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| H A D | pfc-r8a7790.c | 937 PINMUX_IPSR_GPSR(IP2_25_22, A9),
5851 [ 9] = RCAR_GP_PIN(0, 25), /* A9 */
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