1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R8A77990 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 8 * 9 * R8A7796 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2016-2017 Renesas Electronics Corp. 12 */ 13 14#include <linux/errno.h> 15#include <linux/kernel.h> 16 17#include "sh_pfc.h" 18 19#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) 20 21#define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 31 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 34 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \ 38 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \ 39 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ 40 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ 41 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) 42 43#define CPU_ALL_NOGP(fn) \ 44 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 57 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 58 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 59 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \ 60 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) 61 62/* 63 * F_() : just information 64 * FM() : macro for FN_xxx / xxx_MARK 65 */ 66 67/* GPSR0 */ 68#define GPSR0_17 F_(SDA4, IP7_27_24) 69#define GPSR0_16 F_(SCL4, IP7_23_20) 70#define GPSR0_15 F_(D15, IP7_19_16) 71#define GPSR0_14 F_(D14, IP7_15_12) 72#define GPSR0_13 F_(D13, IP7_11_8) 73#define GPSR0_12 F_(D12, IP7_7_4) 74#define GPSR0_11 F_(D11, IP7_3_0) 75#define GPSR0_10 F_(D10, IP6_31_28) 76#define GPSR0_9 F_(D9, IP6_27_24) 77#define GPSR0_8 F_(D8, IP6_23_20) 78#define GPSR0_7 F_(D7, IP6_19_16) 79#define GPSR0_6 F_(D6, IP6_15_12) 80#define GPSR0_5 F_(D5, IP6_11_8) 81#define GPSR0_4 F_(D4, IP6_7_4) 82#define GPSR0_3 F_(D3, IP6_3_0) 83#define GPSR0_2 F_(D2, IP5_31_28) 84#define GPSR0_1 F_(D1, IP5_27_24) 85#define GPSR0_0 F_(D0, IP5_23_20) 86 87/* GPSR1 */ 88#define GPSR1_22 F_(WE0_N, IP5_19_16) 89#define GPSR1_21 F_(CS0_N, IP5_15_12) 90#define GPSR1_20 FM(CLKOUT) 91#define GPSR1_19 F_(A19, IP5_11_8) 92#define GPSR1_18 F_(A18, IP5_7_4) 93#define GPSR1_17 F_(A17, IP5_3_0) 94#define GPSR1_16 F_(A16, IP4_31_28) 95#define GPSR1_15 F_(A15, IP4_27_24) 96#define GPSR1_14 F_(A14, IP4_23_20) 97#define GPSR1_13 F_(A13, IP4_19_16) 98#define GPSR1_12 F_(A12, IP4_15_12) 99#define GPSR1_11 F_(A11, IP4_11_8) 100#define GPSR1_10 F_(A10, IP4_7_4) 101#define GPSR1_9 F_(A9, IP4_3_0) 102#define GPSR1_8 F_(A8, IP3_31_28) 103#define GPSR1_7 F_(A7, IP3_27_24) 104#define GPSR1_6 F_(A6, IP3_23_20) 105#define GPSR1_5 F_(A5, IP3_19_16) 106#define GPSR1_4 F_(A4, IP3_15_12) 107#define GPSR1_3 F_(A3, IP3_11_8) 108#define GPSR1_2 F_(A2, IP3_7_4) 109#define GPSR1_1 F_(A1, IP3_3_0) 110#define GPSR1_0 F_(A0, IP2_31_28) 111 112/* GPSR2 */ 113#define GPSR2_25 F_(EX_WAIT0, IP2_27_24) 114#define GPSR2_24 F_(RD_WR_N, IP2_23_20) 115#define GPSR2_23 F_(RD_N, IP2_19_16) 116#define GPSR2_22 F_(BS_N, IP2_15_12) 117#define GPSR2_21 FM(AVB_PHY_INT) 118#define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) 119#define GPSR2_19 FM(AVB_RD3) 120#define GPSR2_18 F_(AVB_RD2, IP1_31_28) 121#define GPSR2_17 F_(AVB_RD1, IP1_27_24) 122#define GPSR2_16 F_(AVB_RD0, IP1_23_20) 123#define GPSR2_15 FM(AVB_RXC) 124#define GPSR2_14 FM(AVB_RX_CTL) 125#define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) 126#define GPSR2_12 F_(RPC_INT_N, IP1_15_12) 127#define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) 128#define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) 129#define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) 130#define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) 131#define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) 132#define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) 133#define GPSR2_5 FM(QSPI0_SSL) 134#define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) 135#define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) 136#define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) 137#define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) 138#define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) 139 140/* GPSR3 */ 141#define GPSR3_15 F_(SD1_WP, IP11_7_4) 142#define GPSR3_14 F_(SD1_CD, IP11_3_0) 143#define GPSR3_13 F_(SD0_WP, IP10_31_28) 144#define GPSR3_12 F_(SD0_CD, IP10_27_24) 145#define GPSR3_11 F_(SD1_DAT3, IP9_11_8) 146#define GPSR3_10 F_(SD1_DAT2, IP9_7_4) 147#define GPSR3_9 F_(SD1_DAT1, IP9_3_0) 148#define GPSR3_8 F_(SD1_DAT0, IP8_31_28) 149#define GPSR3_7 F_(SD1_CMD, IP8_27_24) 150#define GPSR3_6 F_(SD1_CLK, IP8_23_20) 151#define GPSR3_5 F_(SD0_DAT3, IP8_19_16) 152#define GPSR3_4 F_(SD0_DAT2, IP8_15_12) 153#define GPSR3_3 F_(SD0_DAT1, IP8_11_8) 154#define GPSR3_2 F_(SD0_DAT0, IP8_7_4) 155#define GPSR3_1 F_(SD0_CMD, IP8_3_0) 156#define GPSR3_0 F_(SD0_CLK, IP7_31_28) 157 158/* GPSR4 */ 159#define GPSR4_10 F_(SD3_DS, IP10_23_20) 160#define GPSR4_9 F_(SD3_DAT7, IP10_19_16) 161#define GPSR4_8 F_(SD3_DAT6, IP10_15_12) 162#define GPSR4_7 F_(SD3_DAT5, IP10_11_8) 163#define GPSR4_6 F_(SD3_DAT4, IP10_7_4) 164#define GPSR4_5 F_(SD3_DAT3, IP10_3_0) 165#define GPSR4_4 F_(SD3_DAT2, IP9_31_28) 166#define GPSR4_3 F_(SD3_DAT1, IP9_27_24) 167#define GPSR4_2 F_(SD3_DAT0, IP9_23_20) 168#define GPSR4_1 F_(SD3_CMD, IP9_19_16) 169#define GPSR4_0 F_(SD3_CLK, IP9_15_12) 170 171/* GPSR5 */ 172#define GPSR5_19 F_(MLB_DAT, IP13_23_20) 173#define GPSR5_18 F_(MLB_SIG, IP13_19_16) 174#define GPSR5_17 F_(MLB_CLK, IP13_15_12) 175#define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) 176#define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) 177#define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) 178#define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) 179#define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) 180#define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) 181#define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) 182#define GPSR5_9 F_(RX2_A, IP12_15_12) 183#define GPSR5_8 F_(TX2_A, IP12_11_8) 184#define GPSR5_7 F_(SCK2_A, IP12_7_4) 185#define GPSR5_6 F_(TX1, IP12_3_0) 186#define GPSR5_5 F_(RX1, IP11_31_28) 187#define GPSR5_4 F_(RTS0_N_A, IP11_23_20) 188#define GPSR5_3 F_(CTS0_N_A, IP11_19_16) 189#define GPSR5_2 F_(TX0_A, IP11_15_12) 190#define GPSR5_1 F_(RX0_A, IP11_11_8) 191#define GPSR5_0 F_(SCK0_A, IP11_27_24) 192 193/* GPSR6 */ 194#define GPSR6_17 F_(USB30_PWEN, IP15_27_24) 195#define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) 196#define GPSR6_15 F_(SSI_WS6, IP15_15_12) 197#define GPSR6_14 F_(SSI_SCK6, IP15_11_8) 198#define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) 199#define GPSR6_12 F_(SSI_WS5, IP15_3_0) 200#define GPSR6_11 F_(SSI_SCK5, IP14_31_28) 201#define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) 202#define GPSR6_9 F_(USB30_OVC, IP15_31_28) 203#define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) 204#define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) 205#define GPSR6_6 F_(SSI_WS349, IP14_19_16) 206#define GPSR6_5 F_(SSI_SCK349, IP14_15_12) 207#define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) 208#define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) 209#define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) 210#define GPSR6_1 F_(SSI_WS01239, IP13_31_28) 211#define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) 212 213/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 214#define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217#define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218#define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219#define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227#define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228#define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229#define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230#define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231#define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245#define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 247/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 248#define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249#define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250#define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251#define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252#define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253#define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254#define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255#define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256#define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257#define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258#define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269#define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270#define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274#define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275#define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276#define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277#define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278#define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279#define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 281/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 282#define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283#define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284#define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285#define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286#define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287#define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288#define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289#define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296#define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297#define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298#define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299#define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306#define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307#define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 315/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 316#define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317#define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319#define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320#define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329#define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330#define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331#define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332#define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333#define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334#define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335#define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336#define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337#define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338#define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339#define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340#define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341#define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342#define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343#define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344#define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345#define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346#define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347#define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 349#define PINMUX_GPSR \ 350\ 351 \ 352 \ 353 \ 354 \ 355 \ 356 \ 357 GPSR2_25 \ 358 GPSR2_24 \ 359 GPSR2_23 \ 360 GPSR1_22 GPSR2_22 \ 361 GPSR1_21 GPSR2_21 \ 362 GPSR1_20 GPSR2_20 \ 363 GPSR1_19 GPSR2_19 GPSR5_19 \ 364 GPSR1_18 GPSR2_18 GPSR5_18 \ 365GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ 366GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ 367GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ 368GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ 369GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ 370GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ 371GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ 372GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 373GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 374GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 375GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 376GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 377GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 378GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 379GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ 380GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ 381GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ 382GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 383 384#define PINMUX_IPSR \ 385\ 386FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 387FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 388FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 389FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 390FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 391FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 392FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 393FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 394\ 395FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 396FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 397FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 398FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 399FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 400FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 401FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 402FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 403\ 404FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 405FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 406FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 407FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 408FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 409FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 410FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 411FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 412\ 413FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 414FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 415FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 416FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 417FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 418FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 419FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 420FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 421 422/* The bit numbering in MOD_SEL fields is reversed */ 423#define REV4(f0, f1, f2, f3) f0 f2 f1 f3 424#define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 425 426/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 427#define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0)) 428#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) 429#define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0)) 430#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) 431#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 432#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 433#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) 434#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) 435#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) 436#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) 437#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 438#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 439#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) 440#define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) 441#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 442#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 443#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 444#define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0)) 445#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 446#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 447#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 448#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) 449 450/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 451#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) 452#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 453#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 454#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) 455#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 456#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 457#define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0)) 458#define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0)) 459#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) 460#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) 461#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 462#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 463#define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0)) 464#define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0)) 465#define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0)) 466#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 467#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) 468#define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0)) 469#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 470 471#define PINMUX_MOD_SELS \ 472\ 473 MOD_SEL1_31 \ 474MOD_SEL0_30_29 MOD_SEL1_30 \ 475 MOD_SEL1_29 \ 476MOD_SEL0_28 MOD_SEL1_28 \ 477MOD_SEL0_27_26 \ 478 MOD_SEL1_26 \ 479MOD_SEL0_25 MOD_SEL1_25 \ 480MOD_SEL0_24 MOD_SEL1_24_23_22 \ 481MOD_SEL0_23 \ 482MOD_SEL0_22 \ 483MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ 484MOD_SEL0_19_18_17 MOD_SEL1_18 \ 485 MOD_SEL1_17 \ 486MOD_SEL0_16 MOD_SEL1_16 \ 487MOD_SEL0_15 MOD_SEL1_15 \ 488MOD_SEL0_14 MOD_SEL1_14_13 \ 489MOD_SEL0_13_12 \ 490 MOD_SEL1_12_11 \ 491MOD_SEL0_11_10 \ 492 MOD_SEL1_10_9 \ 493MOD_SEL0_9 \ 494MOD_SEL0_8 MOD_SEL1_8 \ 495MOD_SEL0_7 MOD_SEL1_7 \ 496MOD_SEL0_6_5 MOD_SEL1_6_5 \ 497MOD_SEL0_4 MOD_SEL1_4 \ 498MOD_SEL0_3 \ 499MOD_SEL0_2 \ 500MOD_SEL0_1_0 501 502/* 503 * These pins are not able to be muxed but have other properties 504 * that can be set, such as pull-up/pull-down enable. 505 */ 506#define PINMUX_STATIC \ 507 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ 508 FM(AVB_TD3) \ 509 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ 510 FM(ASEBRK) \ 511 FM(MLB_REF) \ 512 FM(VDDQ_AVB0) 513 514enum { 515 PINMUX_RESERVED = 0, 516 517 PINMUX_DATA_BEGIN, 518 GP_ALL(DATA), 519 PINMUX_DATA_END, 520 521#define F_(x, y) 522#define FM(x) FN_##x, 523 PINMUX_FUNCTION_BEGIN, 524 GP_ALL(FN), 525 PINMUX_GPSR 526 PINMUX_IPSR 527 PINMUX_MOD_SELS 528 PINMUX_FUNCTION_END, 529#undef F_ 530#undef FM 531 532#define F_(x, y) 533#define FM(x) x##_MARK, 534 PINMUX_MARK_BEGIN, 535 PINMUX_GPSR 536 PINMUX_IPSR 537 PINMUX_MOD_SELS 538 PINMUX_STATIC 539 PINMUX_MARK_END, 540#undef F_ 541#undef FM 542}; 543 544static const u16 pinmux_data[] = { 545 PINMUX_DATA_GP_ALL(), 546 547 PINMUX_SINGLE(CLKOUT), 548 PINMUX_SINGLE(AVB_PHY_INT), 549 PINMUX_SINGLE(AVB_RD3), 550 PINMUX_SINGLE(AVB_RXC), 551 PINMUX_SINGLE(AVB_RX_CTL), 552 PINMUX_SINGLE(QSPI0_SSL), 553 554 /* IPSR0 */ 555 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), 556 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), 557 558 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), 559 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), 560 561 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), 562 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), 563 564 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), 565 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), 566 567 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), 568 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), 569 570 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), 571 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), 572 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), 573 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), 574 575 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), 576 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 577 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), 578 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), 579 580 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), 581 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), 582 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), 583 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), 584 585 /* IPSR1 */ 586 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), 587 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), 588 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), 589 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), 590 591 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), 592 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), 593 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), 594 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), 595 596 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), 597 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), 598 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), 599 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), 600 601 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), 602 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), 603 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), 604 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), 605 606 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), 607 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), 608 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), 609 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), 610 611 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), 612 613 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), 614 615 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), 616 617 /* IPSR2 */ 618 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), 619 620 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), 621 622 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), 623 624 PINMUX_IPSR_GPSR(IP2_15_12, BS_N), 625 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), 626 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), 627 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), 628 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), 629 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), 630 631 PINMUX_IPSR_GPSR(IP2_19_16, RD_N), 632 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), 633 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), 634 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), 635 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), 636 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), 637 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), 638 639 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), 640 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), 641 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH), 642 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), 643 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), 644 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), 645 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), 646 647 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), 648 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), 649 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE), 650 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), 651 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), 652 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), 653 654 PINMUX_IPSR_GPSR(IP2_31_28, A0), 655 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), 656 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), 657 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), 658 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), 659 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), 660 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), 661 PINMUX_IPSR_GPSR(IP2_31_28, IERX), 662 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), 663 664 /* IPSR3 */ 665 PINMUX_IPSR_GPSR(IP3_3_0, A1), 666 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), 667 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), 668 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), 669 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), 670 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), 671 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), 672 PINMUX_IPSR_GPSR(IP3_3_0, IETX), 673 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), 674 675 PINMUX_IPSR_GPSR(IP3_7_4, A2), 676 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), 677 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), 678 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), 679 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), 680 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), 681 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), 682 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), 683 684 PINMUX_IPSR_GPSR(IP3_11_8, A3), 685 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), 686 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), 687 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), 688 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), 689 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), 690 PINMUX_IPSR_GPSR(IP3_11_8, IECLK), 691 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), 692 693 PINMUX_IPSR_GPSR(IP3_15_12, A4), 694 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), 695 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), 696 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), 697 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), 698 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 699 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), 700 701 PINMUX_IPSR_GPSR(IP3_19_16, A5), 702 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), 703 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), 704 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), 705 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), 706 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), 707 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), 708 709 PINMUX_IPSR_GPSR(IP3_23_20, A6), 710 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), 711 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), 712 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), 713 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), 714 715 PINMUX_IPSR_GPSR(IP3_27_24, A7), 716 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), 717 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), 718 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), 719 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), 720 721 PINMUX_IPSR_GPSR(IP3_31_28, A8), 722 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), 723 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), 724 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), 725 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), 726 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), 727 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), 728 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), 729 730 /* IPSR4 */ 731 PINMUX_IPSR_GPSR(IP4_3_0, A9), 732 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), 733 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), 734 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), 735 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), 736 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), 737 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), 738 739 PINMUX_IPSR_GPSR(IP4_7_4, A10), 740 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), 741 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), 742 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), 743 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), 744 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), 745 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), 746 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), 747 748 PINMUX_IPSR_GPSR(IP4_11_8, A11), 749 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), 750 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), 751 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), 752 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), 753 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), 754 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), 755 756 PINMUX_IPSR_GPSR(IP4_15_12, A12), 757 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), 758 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), 759 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), 760 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), 761 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), 762 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), 763 764 PINMUX_IPSR_GPSR(IP4_19_16, A13), 765 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), 766 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), 767 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), 768 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), 769 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), 770 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), 771 772 PINMUX_IPSR_GPSR(IP4_23_20, A14), 773 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), 774 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), 775 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), 776 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), 777 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), 778 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), 779 780 PINMUX_IPSR_GPSR(IP4_27_24, A15), 781 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), 782 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), 783 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), 784 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), 785 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), 786 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), 787 788 PINMUX_IPSR_GPSR(IP4_31_28, A16), 789 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), 790 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), 791 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), 792 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), 793 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), 794 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), 795 796 /* IPSR5 */ 797 PINMUX_IPSR_GPSR(IP5_3_0, A17), 798 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 799 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), 800 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), 801 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), 802 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), 803 804 PINMUX_IPSR_GPSR(IP5_7_4, A18), 805 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 806 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), 807 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), 808 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), 809 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), 810 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), 811 812 PINMUX_IPSR_GPSR(IP5_11_8, A19), 813 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 814 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), 815 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), 816 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), 817 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), 818 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), 819 820 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), 821 PINMUX_IPSR_GPSR(IP5_15_12, SCL5), 822 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), 823 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), 824 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), 825 826 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), 827 PINMUX_IPSR_GPSR(IP5_19_16, SDA5), 828 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), 829 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), 830 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), 831 832 PINMUX_IPSR_GPSR(IP5_23_20, D0), 833 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), 834 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), 835 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), 836 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), 837 838 PINMUX_IPSR_GPSR(IP5_27_24, D1), 839 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), 840 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), 841 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), 842 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), 843 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), 844 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), 845 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), 846 847 PINMUX_IPSR_GPSR(IP5_31_28, D2), 848 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), 849 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), 850 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), 851 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), 852 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), 853 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), 854 855 /* IPSR6 */ 856 PINMUX_IPSR_GPSR(IP6_3_0, D3), 857 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), 858 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), 859 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), 860 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), 861 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), 862 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), 863 864 PINMUX_IPSR_GPSR(IP6_7_4, D4), 865 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), 866 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), 867 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), 868 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), 869 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), 870 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), 871 872 PINMUX_IPSR_GPSR(IP6_11_8, D5), 873 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), 874 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), 875 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), 876 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), 877 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), 878 879 PINMUX_IPSR_GPSR(IP6_15_12, D6), 880 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), 881 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), 882 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), 883 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), 884 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), 885 886 PINMUX_IPSR_GPSR(IP6_19_16, D7), 887 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), 888 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), 889 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), 890 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), 891 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), 892 893 PINMUX_IPSR_GPSR(IP6_23_20, D8), 894 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), 895 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), 896 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), 897 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), 898 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), 899 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), 900 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), 901 902 PINMUX_IPSR_GPSR(IP6_27_24, D9), 903 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), 904 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), 905 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), 906 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), 907 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), 908 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), 909 910 PINMUX_IPSR_GPSR(IP6_31_28, D10), 911 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), 912 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), 913 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), 914 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), 915 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), 916 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), 917 918 /* IPSR7 */ 919 PINMUX_IPSR_GPSR(IP7_3_0, D11), 920 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), 921 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), 922 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), 923 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), 924 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), 925 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), 926 927 PINMUX_IPSR_GPSR(IP7_7_4, D12), 928 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), 929 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), 930 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), 931 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), 932 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), 933 934 PINMUX_IPSR_GPSR(IP7_11_8, D13), 935 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), 936 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), 937 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), 938 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), 939 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), 940 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), 941 942 PINMUX_IPSR_GPSR(IP7_15_12, D14), 943 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), 944 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), 945 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), 946 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), 947 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), 948 949 PINMUX_IPSR_GPSR(IP7_19_16, D15), 950 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), 951 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), 952 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), 953 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), 954 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), 955 956 PINMUX_IPSR_GPSR(IP7_23_20, SCL4), 957 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), 958 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), 959 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), 960 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), 961 PINMUX_IPSR_GPSR(IP7_23_20, QCLK), 962 963 PINMUX_IPSR_GPSR(IP7_27_24, SDA4), 964 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), 965 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), 966 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), 967 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), 968 969 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), 970 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), 971 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), 972 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), 973 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), 974 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), 975 976 /* IPSR8 */ 977 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), 978 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), 979 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), 980 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), 981 982 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), 983 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), 984 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), 985 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), 986 987 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), 988 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), 989 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), 990 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), 991 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), 992 993 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), 994 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), 995 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), 996 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), 997 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), 998 999 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), 1000 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), 1001 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), 1002 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), 1003 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), 1004 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), 1005 1006 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), 1007 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1008 1009 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), 1010 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1011 1012 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), 1013 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), 1014 1015 /* IPSR9 */ 1016 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), 1017 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), 1018 1019 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), 1020 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), 1021 1022 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), 1023 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), 1024 1025 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), 1026 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), 1027 1028 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), 1029 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), 1030 1031 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), 1032 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), 1033 1034 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), 1035 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), 1036 1037 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), 1038 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), 1039 1040 /* IPSR10 */ 1041 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), 1042 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), 1043 1044 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), 1045 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), 1046 1047 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), 1048 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), 1049 1050 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), 1051 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), 1052 1053 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), 1054 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), 1055 1056 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), 1057 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), 1058 1059 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), 1060 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), 1061 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), 1062 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1063 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), 1064 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), 1065 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), 1066 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), 1067 1068 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), 1069 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), 1070 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), 1071 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), 1072 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), 1073 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), 1074 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), 1075 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), 1076 1077 /* IPSR11 */ 1078 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), 1079 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), 1080 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), 1081 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), 1082 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), 1083 1084 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), 1085 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), 1086 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), 1087 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), 1088 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), 1089 1090 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), 1091 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), 1092 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), 1093 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), 1094 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), 1095 1096 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), 1097 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), 1098 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), 1099 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), 1100 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), 1101 1102 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), 1103 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), 1104 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), 1105 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), 1106 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), 1107 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), 1108 1109 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), 1110 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), 1111 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), 1112 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), 1113 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), 1114 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), 1115 1116 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), 1117 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), 1118 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), 1119 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), 1120 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1121 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), 1122 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), 1123 1124 PINMUX_IPSR_GPSR(IP11_31_28, RX1), 1125 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), 1126 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), 1127 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), 1128 1129 /* IPSR12 */ 1130 PINMUX_IPSR_GPSR(IP12_3_0, TX1), 1131 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), 1132 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), 1133 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), 1134 1135 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0), 1136 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), 1137 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), 1138 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), 1139 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), 1140 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), 1141 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), 1142 1143 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0), 1144 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), 1145 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), 1146 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), 1147 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), 1148 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), 1149 1150 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0), 1151 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), 1152 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), 1153 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), 1154 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), 1155 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), 1156 1157 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), 1158 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), 1159 1160 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), 1161 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), 1162 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1), 1163 1164 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), 1165 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), 1166 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1), 1167 1168 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), 1169 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), 1170 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), 1171 1172 /* IPSR13 */ 1173 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), 1174 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), 1175 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), 1176 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), 1177 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), 1178 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), 1179 1180 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), 1181 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), 1182 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), 1183 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), 1184 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), 1185 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), 1186 1187 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), 1188 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), 1189 PINMUX_IPSR_GPSR(IP13_11_8, SCK1), 1190 1191 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), 1192 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), 1193 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), 1194 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), 1195 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), 1196 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), 1197 1198 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), 1199 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), 1200 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), 1201 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), 1202 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), 1203 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), 1204 1205 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), 1206 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), 1207 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), 1208 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), 1209 1210 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), 1211 1212 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), 1213 1214 /* IPSR14 */ 1215 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), 1216 1217 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), 1218 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), 1219 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), 1220 1221 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), 1222 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), 1223 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), 1224 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), 1225 1226 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), 1227 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), 1228 1229 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), 1230 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), 1231 1232 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), 1233 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), 1234 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), 1235 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), 1236 1237 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), 1238 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), 1239 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), 1240 1241 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), 1242 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), 1243 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), 1244 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), 1245 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), 1246 1247 /* IPSR15 */ 1248 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), 1249 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), 1250 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), 1251 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), 1252 1253 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), 1254 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), 1255 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), 1256 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), 1257 1258 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), 1259 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), 1260 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), 1261 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), 1262 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), 1263 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), 1264 1265 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), 1266 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1267 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), 1268 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), 1269 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), 1270 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), 1271 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), 1272 1273 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), 1274 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1275 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), 1276 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), 1277 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), 1278 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), 1279 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), 1280 1281 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), 1282 1283 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), 1284 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), 1285 1286 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), 1287 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), 1288 1289/* 1290 * Static pins can not be muxed between different functions but 1291 * still need mark entries in the pinmux list. Add each static 1292 * pin to the list without an associated function. The sh-pfc 1293 * core will do the right thing and skip trying to mux the pin 1294 * while still applying configuration to it. 1295 */ 1296#define FM(x) PINMUX_DATA(x##_MARK, 0), 1297 PINMUX_STATIC 1298#undef FM 1299}; 1300 1301/* 1302 * Pins not associated with a GPIO port. 1303 */ 1304enum { 1305 GP_ASSIGN_LAST(), 1306 NOGP_ALL(), 1307}; 1308 1309static const struct sh_pfc_pin pinmux_pins[] = { 1310 PINMUX_GPIO_GP_ALL(), 1311 PINMUX_NOGP_ALL(), 1312}; 1313 1314/* - AUDIO CLOCK ------------------------------------------------------------ */ 1315static const unsigned int audio_clk_a_pins[] = { 1316 /* CLK A */ 1317 RCAR_GP_PIN(6, 8), 1318}; 1319 1320static const unsigned int audio_clk_a_mux[] = { 1321 AUDIO_CLKA_MARK, 1322}; 1323 1324static const unsigned int audio_clk_b_a_pins[] = { 1325 /* CLK B_A */ 1326 RCAR_GP_PIN(5, 7), 1327}; 1328 1329static const unsigned int audio_clk_b_a_mux[] = { 1330 AUDIO_CLKB_A_MARK, 1331}; 1332 1333static const unsigned int audio_clk_b_b_pins[] = { 1334 /* CLK B_B */ 1335 RCAR_GP_PIN(6, 7), 1336}; 1337 1338static const unsigned int audio_clk_b_b_mux[] = { 1339 AUDIO_CLKB_B_MARK, 1340}; 1341 1342static const unsigned int audio_clk_b_c_pins[] = { 1343 /* CLK B_C */ 1344 RCAR_GP_PIN(6, 13), 1345}; 1346 1347static const unsigned int audio_clk_b_c_mux[] = { 1348 AUDIO_CLKB_C_MARK, 1349}; 1350 1351static const unsigned int audio_clk_c_a_pins[] = { 1352 /* CLK C_A */ 1353 RCAR_GP_PIN(5, 16), 1354}; 1355 1356static const unsigned int audio_clk_c_a_mux[] = { 1357 AUDIO_CLKC_A_MARK, 1358}; 1359 1360static const unsigned int audio_clk_c_b_pins[] = { 1361 /* CLK C_B */ 1362 RCAR_GP_PIN(6, 3), 1363}; 1364 1365static const unsigned int audio_clk_c_b_mux[] = { 1366 AUDIO_CLKC_B_MARK, 1367}; 1368 1369static const unsigned int audio_clk_c_c_pins[] = { 1370 /* CLK C_C */ 1371 RCAR_GP_PIN(6, 14), 1372}; 1373 1374static const unsigned int audio_clk_c_c_mux[] = { 1375 AUDIO_CLKC_C_MARK, 1376}; 1377 1378static const unsigned int audio_clkout_a_pins[] = { 1379 /* CLKOUT_A */ 1380 RCAR_GP_PIN(5, 3), 1381}; 1382 1383static const unsigned int audio_clkout_a_mux[] = { 1384 AUDIO_CLKOUT_A_MARK, 1385}; 1386 1387static const unsigned int audio_clkout_b_pins[] = { 1388 /* CLKOUT_B */ 1389 RCAR_GP_PIN(5, 13), 1390}; 1391 1392static const unsigned int audio_clkout_b_mux[] = { 1393 AUDIO_CLKOUT_B_MARK, 1394}; 1395 1396static const unsigned int audio_clkout1_a_pins[] = { 1397 /* CLKOUT1_A */ 1398 RCAR_GP_PIN(5, 4), 1399}; 1400 1401static const unsigned int audio_clkout1_a_mux[] = { 1402 AUDIO_CLKOUT1_A_MARK, 1403}; 1404 1405static const unsigned int audio_clkout1_b_pins[] = { 1406 /* CLKOUT1_B */ 1407 RCAR_GP_PIN(5, 5), 1408}; 1409 1410static const unsigned int audio_clkout1_b_mux[] = { 1411 AUDIO_CLKOUT1_B_MARK, 1412}; 1413 1414static const unsigned int audio_clkout1_c_pins[] = { 1415 /* CLKOUT1_C */ 1416 RCAR_GP_PIN(6, 7), 1417}; 1418 1419static const unsigned int audio_clkout1_c_mux[] = { 1420 AUDIO_CLKOUT1_C_MARK, 1421}; 1422 1423static const unsigned int audio_clkout2_a_pins[] = { 1424 /* CLKOUT2_A */ 1425 RCAR_GP_PIN(5, 8), 1426}; 1427 1428static const unsigned int audio_clkout2_a_mux[] = { 1429 AUDIO_CLKOUT2_A_MARK, 1430}; 1431 1432static const unsigned int audio_clkout2_b_pins[] = { 1433 /* CLKOUT2_B */ 1434 RCAR_GP_PIN(6, 4), 1435}; 1436 1437static const unsigned int audio_clkout2_b_mux[] = { 1438 AUDIO_CLKOUT2_B_MARK, 1439}; 1440 1441static const unsigned int audio_clkout2_c_pins[] = { 1442 /* CLKOUT2_C */ 1443 RCAR_GP_PIN(6, 15), 1444}; 1445 1446static const unsigned int audio_clkout2_c_mux[] = { 1447 AUDIO_CLKOUT2_C_MARK, 1448}; 1449 1450static const unsigned int audio_clkout3_a_pins[] = { 1451 /* CLKOUT3_A */ 1452 RCAR_GP_PIN(5, 9), 1453}; 1454 1455static const unsigned int audio_clkout3_a_mux[] = { 1456 AUDIO_CLKOUT3_A_MARK, 1457}; 1458 1459static const unsigned int audio_clkout3_b_pins[] = { 1460 /* CLKOUT3_B */ 1461 RCAR_GP_PIN(5, 6), 1462}; 1463 1464static const unsigned int audio_clkout3_b_mux[] = { 1465 AUDIO_CLKOUT3_B_MARK, 1466}; 1467 1468static const unsigned int audio_clkout3_c_pins[] = { 1469 /* CLKOUT3_C */ 1470 RCAR_GP_PIN(6, 16), 1471}; 1472 1473static const unsigned int audio_clkout3_c_mux[] = { 1474 AUDIO_CLKOUT3_C_MARK, 1475}; 1476 1477/* - EtherAVB --------------------------------------------------------------- */ 1478static const unsigned int avb_link_pins[] = { 1479 /* AVB_LINK */ 1480 RCAR_GP_PIN(2, 23), 1481}; 1482 1483static const unsigned int avb_link_mux[] = { 1484 AVB_LINK_MARK, 1485}; 1486 1487static const unsigned int avb_magic_pins[] = { 1488 /* AVB_MAGIC */ 1489 RCAR_GP_PIN(2, 22), 1490}; 1491 1492static const unsigned int avb_magic_mux[] = { 1493 AVB_MAGIC_MARK, 1494}; 1495 1496static const unsigned int avb_phy_int_pins[] = { 1497 /* AVB_PHY_INT */ 1498 RCAR_GP_PIN(2, 21), 1499}; 1500 1501static const unsigned int avb_phy_int_mux[] = { 1502 AVB_PHY_INT_MARK, 1503}; 1504 1505static const unsigned int avb_mii_pins[] = { 1506 /* 1507 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1508 * AVB_RD1, AVB_RD2, AVB_RD3, 1509 * AVB_TXCREFCLK 1510 */ 1511 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 1512 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 1513 RCAR_GP_PIN(2, 20), 1514}; 1515 1516static const unsigned int avb_mii_mux[] = { 1517 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1518 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1519 AVB_TXCREFCLK_MARK, 1520}; 1521 1522static const unsigned int avb_avtp_pps_pins[] = { 1523 /* AVB_AVTP_PPS */ 1524 RCAR_GP_PIN(1, 2), 1525}; 1526 1527static const unsigned int avb_avtp_pps_mux[] = { 1528 AVB_AVTP_PPS_MARK, 1529}; 1530 1531static const unsigned int avb_avtp_match_pins[] = { 1532 /* AVB_AVTP_MATCH */ 1533 RCAR_GP_PIN(2, 24), 1534}; 1535 1536static const unsigned int avb_avtp_match_mux[] = { 1537 AVB_AVTP_MATCH_MARK, 1538}; 1539 1540static const unsigned int avb_avtp_capture_pins[] = { 1541 /* AVB_AVTP_CAPTURE */ 1542 RCAR_GP_PIN(2, 25), 1543}; 1544 1545static const unsigned int avb_avtp_capture_mux[] = { 1546 AVB_AVTP_CAPTURE_MARK, 1547}; 1548 1549/* - CAN ------------------------------------------------------------------ */ 1550static const unsigned int can0_data_pins[] = { 1551 /* TX, RX */ 1552 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1553}; 1554 1555static const unsigned int can0_data_mux[] = { 1556 CAN0_TX_MARK, CAN0_RX_MARK, 1557}; 1558 1559static const unsigned int can1_data_pins[] = { 1560 /* TX, RX */ 1561 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1562}; 1563 1564static const unsigned int can1_data_mux[] = { 1565 CAN1_TX_MARK, CAN1_RX_MARK, 1566}; 1567 1568/* - CAN Clock -------------------------------------------------------------- */ 1569static const unsigned int can_clk_pins[] = { 1570 /* CLK */ 1571 RCAR_GP_PIN(0, 14), 1572}; 1573 1574static const unsigned int can_clk_mux[] = { 1575 CAN_CLK_MARK, 1576}; 1577 1578/* - CAN FD --------------------------------------------------------------- */ 1579static const unsigned int canfd0_data_pins[] = { 1580 /* TX, RX */ 1581 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1582}; 1583 1584static const unsigned int canfd0_data_mux[] = { 1585 CANFD0_TX_MARK, CANFD0_RX_MARK, 1586}; 1587 1588static const unsigned int canfd1_data_pins[] = { 1589 /* TX, RX */ 1590 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1591}; 1592 1593static const unsigned int canfd1_data_mux[] = { 1594 CANFD1_TX_MARK, CANFD1_RX_MARK, 1595}; 1596 1597#ifdef CONFIG_PINCTRL_PFC_R8A77990 1598/* - DRIF0 --------------------------------------------------------------- */ 1599static const unsigned int drif0_ctrl_a_pins[] = { 1600 /* CLK, SYNC */ 1601 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19), 1602}; 1603 1604static const unsigned int drif0_ctrl_a_mux[] = { 1605 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1606}; 1607 1608static const unsigned int drif0_data0_a_pins[] = { 1609 /* D0 */ 1610 RCAR_GP_PIN(5, 17), 1611}; 1612 1613static const unsigned int drif0_data0_a_mux[] = { 1614 RIF0_D0_A_MARK, 1615}; 1616 1617static const unsigned int drif0_data1_a_pins[] = { 1618 /* D1 */ 1619 RCAR_GP_PIN(5, 18), 1620}; 1621 1622static const unsigned int drif0_data1_a_mux[] = { 1623 RIF0_D1_A_MARK, 1624}; 1625 1626static const unsigned int drif0_ctrl_b_pins[] = { 1627 /* CLK, SYNC */ 1628 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 1629}; 1630 1631static const unsigned int drif0_ctrl_b_mux[] = { 1632 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1633}; 1634 1635static const unsigned int drif0_data0_b_pins[] = { 1636 /* D0 */ 1637 RCAR_GP_PIN(3, 13), 1638}; 1639 1640static const unsigned int drif0_data0_b_mux[] = { 1641 RIF0_D0_B_MARK, 1642}; 1643 1644static const unsigned int drif0_data1_b_pins[] = { 1645 /* D1 */ 1646 RCAR_GP_PIN(3, 14), 1647}; 1648 1649static const unsigned int drif0_data1_b_mux[] = { 1650 RIF0_D1_B_MARK, 1651}; 1652 1653/* - DRIF1 --------------------------------------------------------------- */ 1654static const unsigned int drif1_ctrl_pins[] = { 1655 /* CLK, SYNC */ 1656 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1), 1657}; 1658 1659static const unsigned int drif1_ctrl_mux[] = { 1660 RIF1_CLK_MARK, RIF1_SYNC_MARK, 1661}; 1662 1663static const unsigned int drif1_data0_pins[] = { 1664 /* D0 */ 1665 RCAR_GP_PIN(5, 2), 1666}; 1667 1668static const unsigned int drif1_data0_mux[] = { 1669 RIF1_D0_MARK, 1670}; 1671 1672static const unsigned int drif1_data1_pins[] = { 1673 /* D1 */ 1674 RCAR_GP_PIN(5, 3), 1675}; 1676 1677static const unsigned int drif1_data1_mux[] = { 1678 RIF1_D1_MARK, 1679}; 1680 1681/* - DRIF2 --------------------------------------------------------------- */ 1682static const unsigned int drif2_ctrl_a_pins[] = { 1683 /* CLK, SYNC */ 1684 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1685}; 1686 1687static const unsigned int drif2_ctrl_a_mux[] = { 1688 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1689}; 1690 1691static const unsigned int drif2_data0_a_pins[] = { 1692 /* D0 */ 1693 RCAR_GP_PIN(2, 8), 1694}; 1695 1696static const unsigned int drif2_data0_a_mux[] = { 1697 RIF2_D0_A_MARK, 1698}; 1699 1700static const unsigned int drif2_data1_a_pins[] = { 1701 /* D1 */ 1702 RCAR_GP_PIN(2, 9), 1703}; 1704 1705static const unsigned int drif2_data1_a_mux[] = { 1706 RIF2_D1_A_MARK, 1707}; 1708 1709static const unsigned int drif2_ctrl_b_pins[] = { 1710 /* CLK, SYNC */ 1711 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 1712}; 1713 1714static const unsigned int drif2_ctrl_b_mux[] = { 1715 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1716}; 1717 1718static const unsigned int drif2_data0_b_pins[] = { 1719 /* D0 */ 1720 RCAR_GP_PIN(1, 6), 1721}; 1722 1723static const unsigned int drif2_data0_b_mux[] = { 1724 RIF2_D0_B_MARK, 1725}; 1726 1727static const unsigned int drif2_data1_b_pins[] = { 1728 /* D1 */ 1729 RCAR_GP_PIN(1, 7), 1730}; 1731 1732static const unsigned int drif2_data1_b_mux[] = { 1733 RIF2_D1_B_MARK, 1734}; 1735 1736/* - DRIF3 --------------------------------------------------------------- */ 1737static const unsigned int drif3_ctrl_a_pins[] = { 1738 /* CLK, SYNC */ 1739 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1740}; 1741 1742static const unsigned int drif3_ctrl_a_mux[] = { 1743 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 1744}; 1745 1746static const unsigned int drif3_data0_a_pins[] = { 1747 /* D0 */ 1748 RCAR_GP_PIN(2, 12), 1749}; 1750 1751static const unsigned int drif3_data0_a_mux[] = { 1752 RIF3_D0_A_MARK, 1753}; 1754 1755static const unsigned int drif3_data1_a_pins[] = { 1756 /* D1 */ 1757 RCAR_GP_PIN(2, 13), 1758}; 1759 1760static const unsigned int drif3_data1_a_mux[] = { 1761 RIF3_D1_A_MARK, 1762}; 1763 1764static const unsigned int drif3_ctrl_b_pins[] = { 1765 /* CLK, SYNC */ 1766 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 1767}; 1768 1769static const unsigned int drif3_ctrl_b_mux[] = { 1770 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 1771}; 1772 1773static const unsigned int drif3_data0_b_pins[] = { 1774 /* D0 */ 1775 RCAR_GP_PIN(0, 10), 1776}; 1777 1778static const unsigned int drif3_data0_b_mux[] = { 1779 RIF3_D0_B_MARK, 1780}; 1781 1782static const unsigned int drif3_data1_b_pins[] = { 1783 /* D1 */ 1784 RCAR_GP_PIN(0, 11), 1785}; 1786 1787static const unsigned int drif3_data1_b_mux[] = { 1788 RIF3_D1_B_MARK, 1789}; 1790#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 1791 1792/* - DU --------------------------------------------------------------------- */ 1793static const unsigned int du_rgb666_pins[] = { 1794 /* R[7:2], G[7:2], B[7:2] */ 1795 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1796 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1797 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1798 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1799 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1800 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1801}; 1802static const unsigned int du_rgb666_mux[] = { 1803 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1804 DU_DR3_MARK, DU_DR2_MARK, 1805 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1806 DU_DG3_MARK, DU_DG2_MARK, 1807 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1808 DU_DB3_MARK, DU_DB2_MARK, 1809}; 1810static const unsigned int du_rgb888_pins[] = { 1811 /* R[7:0], G[7:0], B[7:0] */ 1812 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1813 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1814 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1815 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1816 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1817 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 1818 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1819 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1820 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1821}; 1822static const unsigned int du_rgb888_mux[] = { 1823 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1824 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 1825 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1826 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 1827 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1828 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 1829}; 1830static const unsigned int du_clk_in_0_pins[] = { 1831 /* CLKIN0 */ 1832 RCAR_GP_PIN(0, 16), 1833}; 1834static const unsigned int du_clk_in_0_mux[] = { 1835 DU_DOTCLKIN0_MARK 1836}; 1837static const unsigned int du_clk_in_1_pins[] = { 1838 /* CLKIN1 */ 1839 RCAR_GP_PIN(1, 1), 1840}; 1841static const unsigned int du_clk_in_1_mux[] = { 1842 DU_DOTCLKIN1_MARK 1843}; 1844static const unsigned int du_clk_out_0_pins[] = { 1845 /* CLKOUT */ 1846 RCAR_GP_PIN(1, 3), 1847}; 1848static const unsigned int du_clk_out_0_mux[] = { 1849 DU_DOTCLKOUT0_MARK 1850}; 1851static const unsigned int du_sync_pins[] = { 1852 /* VSYNC, HSYNC */ 1853 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 1854}; 1855static const unsigned int du_sync_mux[] = { 1856 DU_VSYNC_MARK, DU_HSYNC_MARK 1857}; 1858static const unsigned int du_disp_cde_pins[] = { 1859 /* DISP_CDE */ 1860 RCAR_GP_PIN(1, 1), 1861}; 1862static const unsigned int du_disp_cde_mux[] = { 1863 DU_DISP_CDE_MARK, 1864}; 1865static const unsigned int du_cde_pins[] = { 1866 /* CDE */ 1867 RCAR_GP_PIN(1, 0), 1868}; 1869static const unsigned int du_cde_mux[] = { 1870 DU_CDE_MARK, 1871}; 1872static const unsigned int du_disp_pins[] = { 1873 /* DISP */ 1874 RCAR_GP_PIN(1, 2), 1875}; 1876static const unsigned int du_disp_mux[] = { 1877 DU_DISP_MARK, 1878}; 1879 1880/* - HSCIF0 --------------------------------------------------*/ 1881static const unsigned int hscif0_data_a_pins[] = { 1882 /* RX, TX */ 1883 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 1884}; 1885 1886static const unsigned int hscif0_data_a_mux[] = { 1887 HRX0_A_MARK, HTX0_A_MARK, 1888}; 1889 1890static const unsigned int hscif0_clk_a_pins[] = { 1891 /* SCK */ 1892 RCAR_GP_PIN(5, 7), 1893}; 1894 1895static const unsigned int hscif0_clk_a_mux[] = { 1896 HSCK0_A_MARK, 1897}; 1898 1899static const unsigned int hscif0_ctrl_a_pins[] = { 1900 /* RTS, CTS */ 1901 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1902}; 1903 1904static const unsigned int hscif0_ctrl_a_mux[] = { 1905 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1906}; 1907 1908static const unsigned int hscif0_data_b_pins[] = { 1909 /* RX, TX */ 1910 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 1911}; 1912 1913static const unsigned int hscif0_data_b_mux[] = { 1914 HRX0_B_MARK, HTX0_B_MARK, 1915}; 1916 1917static const unsigned int hscif0_clk_b_pins[] = { 1918 /* SCK */ 1919 RCAR_GP_PIN(6, 13), 1920}; 1921 1922static const unsigned int hscif0_clk_b_mux[] = { 1923 HSCK0_B_MARK, 1924}; 1925 1926/* - HSCIF1 ------------------------------------------------- */ 1927static const unsigned int hscif1_data_a_pins[] = { 1928 /* RX, TX */ 1929 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1930}; 1931 1932static const unsigned int hscif1_data_a_mux[] = { 1933 HRX1_A_MARK, HTX1_A_MARK, 1934}; 1935 1936static const unsigned int hscif1_clk_a_pins[] = { 1937 /* SCK */ 1938 RCAR_GP_PIN(5, 0), 1939}; 1940 1941static const unsigned int hscif1_clk_a_mux[] = { 1942 HSCK1_A_MARK, 1943}; 1944 1945static const unsigned int hscif1_data_b_pins[] = { 1946 /* RX, TX */ 1947 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 1948}; 1949 1950static const unsigned int hscif1_data_b_mux[] = { 1951 HRX1_B_MARK, HTX1_B_MARK, 1952}; 1953 1954static const unsigned int hscif1_clk_b_pins[] = { 1955 /* SCK */ 1956 RCAR_GP_PIN(3, 0), 1957}; 1958 1959static const unsigned int hscif1_clk_b_mux[] = { 1960 HSCK1_B_MARK, 1961}; 1962 1963static const unsigned int hscif1_ctrl_b_pins[] = { 1964 /* RTS, CTS */ 1965 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 1966}; 1967 1968static const unsigned int hscif1_ctrl_b_mux[] = { 1969 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1970}; 1971 1972/* - HSCIF2 ------------------------------------------------- */ 1973static const unsigned int hscif2_data_a_pins[] = { 1974 /* RX, TX */ 1975 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 1976}; 1977 1978static const unsigned int hscif2_data_a_mux[] = { 1979 HRX2_A_MARK, HTX2_A_MARK, 1980}; 1981 1982static const unsigned int hscif2_clk_a_pins[] = { 1983 /* SCK */ 1984 RCAR_GP_PIN(6, 14), 1985}; 1986 1987static const unsigned int hscif2_clk_a_mux[] = { 1988 HSCK2_A_MARK, 1989}; 1990 1991static const unsigned int hscif2_ctrl_a_pins[] = { 1992 /* RTS, CTS */ 1993 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 1994}; 1995 1996static const unsigned int hscif2_ctrl_a_mux[] = { 1997 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 1998}; 1999 2000static const unsigned int hscif2_data_b_pins[] = { 2001 /* RX, TX */ 2002 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2003}; 2004 2005static const unsigned int hscif2_data_b_mux[] = { 2006 HRX2_B_MARK, HTX2_B_MARK, 2007}; 2008 2009/* - HSCIF3 ------------------------------------------------*/ 2010static const unsigned int hscif3_data_a_pins[] = { 2011 /* RX, TX */ 2012 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2013}; 2014 2015static const unsigned int hscif3_data_a_mux[] = { 2016 HRX3_A_MARK, HTX3_A_MARK, 2017}; 2018 2019static const unsigned int hscif3_data_b_pins[] = { 2020 /* RX, TX */ 2021 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2022}; 2023 2024static const unsigned int hscif3_data_b_mux[] = { 2025 HRX3_B_MARK, HTX3_B_MARK, 2026}; 2027 2028static const unsigned int hscif3_clk_b_pins[] = { 2029 /* SCK */ 2030 RCAR_GP_PIN(0, 4), 2031}; 2032 2033static const unsigned int hscif3_clk_b_mux[] = { 2034 HSCK3_B_MARK, 2035}; 2036 2037static const unsigned int hscif3_data_c_pins[] = { 2038 /* RX, TX */ 2039 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), 2040}; 2041 2042static const unsigned int hscif3_data_c_mux[] = { 2043 HRX3_C_MARK, HTX3_C_MARK, 2044}; 2045 2046static const unsigned int hscif3_clk_c_pins[] = { 2047 /* SCK */ 2048 RCAR_GP_PIN(2, 11), 2049}; 2050 2051static const unsigned int hscif3_clk_c_mux[] = { 2052 HSCK3_C_MARK, 2053}; 2054 2055static const unsigned int hscif3_ctrl_c_pins[] = { 2056 /* RTS, CTS */ 2057 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), 2058}; 2059 2060static const unsigned int hscif3_ctrl_c_mux[] = { 2061 HRTS3_N_C_MARK, HCTS3_N_C_MARK, 2062}; 2063 2064static const unsigned int hscif3_data_d_pins[] = { 2065 /* RX, TX */ 2066 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), 2067}; 2068 2069static const unsigned int hscif3_data_d_mux[] = { 2070 HRX3_D_MARK, HTX3_D_MARK, 2071}; 2072 2073static const unsigned int hscif3_data_e_pins[] = { 2074 /* RX, TX */ 2075 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2076}; 2077 2078static const unsigned int hscif3_data_e_mux[] = { 2079 HRX3_E_MARK, HTX3_E_MARK, 2080}; 2081 2082static const unsigned int hscif3_ctrl_e_pins[] = { 2083 /* RTS, CTS */ 2084 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), 2085}; 2086 2087static const unsigned int hscif3_ctrl_e_mux[] = { 2088 HRTS3_N_E_MARK, HCTS3_N_E_MARK, 2089}; 2090 2091/* - HSCIF4 -------------------------------------------------- */ 2092static const unsigned int hscif4_data_a_pins[] = { 2093 /* RX, TX */ 2094 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 2095}; 2096 2097static const unsigned int hscif4_data_a_mux[] = { 2098 HRX4_A_MARK, HTX4_A_MARK, 2099}; 2100 2101static const unsigned int hscif4_clk_a_pins[] = { 2102 /* SCK */ 2103 RCAR_GP_PIN(2, 0), 2104}; 2105 2106static const unsigned int hscif4_clk_a_mux[] = { 2107 HSCK4_A_MARK, 2108}; 2109 2110static const unsigned int hscif4_ctrl_a_pins[] = { 2111 /* RTS, CTS */ 2112 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 2113}; 2114 2115static const unsigned int hscif4_ctrl_a_mux[] = { 2116 HRTS4_N_A_MARK, HCTS4_N_A_MARK, 2117}; 2118 2119static const unsigned int hscif4_data_b_pins[] = { 2120 /* RX, TX */ 2121 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2122}; 2123 2124static const unsigned int hscif4_data_b_mux[] = { 2125 HRX4_B_MARK, HTX4_B_MARK, 2126}; 2127 2128static const unsigned int hscif4_clk_b_pins[] = { 2129 /* SCK */ 2130 RCAR_GP_PIN(2, 6), 2131}; 2132 2133static const unsigned int hscif4_clk_b_mux[] = { 2134 HSCK4_B_MARK, 2135}; 2136 2137static const unsigned int hscif4_data_c_pins[] = { 2138 /* RX, TX */ 2139 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2140}; 2141 2142static const unsigned int hscif4_data_c_mux[] = { 2143 HRX4_C_MARK, HTX4_C_MARK, 2144}; 2145 2146static const unsigned int hscif4_data_d_pins[] = { 2147 /* RX, TX */ 2148 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 2149}; 2150 2151static const unsigned int hscif4_data_d_mux[] = { 2152 HRX4_D_MARK, HTX4_D_MARK, 2153}; 2154 2155static const unsigned int hscif4_data_e_pins[] = { 2156 /* RX, TX */ 2157 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2158}; 2159 2160static const unsigned int hscif4_data_e_mux[] = { 2161 HRX4_E_MARK, HTX4_E_MARK, 2162}; 2163 2164/* - I2C -------------------------------------------------------------------- */ 2165static const unsigned int i2c1_a_pins[] = { 2166 /* SCL, SDA */ 2167 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2168}; 2169 2170static const unsigned int i2c1_a_mux[] = { 2171 SCL1_A_MARK, SDA1_A_MARK, 2172}; 2173 2174static const unsigned int i2c1_b_pins[] = { 2175 /* SCL, SDA */ 2176 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2177}; 2178 2179static const unsigned int i2c1_b_mux[] = { 2180 SCL1_B_MARK, SDA1_B_MARK, 2181}; 2182 2183static const unsigned int i2c1_c_pins[] = { 2184 /* SCL, SDA */ 2185 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), 2186}; 2187 2188static const unsigned int i2c1_c_mux[] = { 2189 SCL1_C_MARK, SDA1_C_MARK, 2190}; 2191 2192static const unsigned int i2c1_d_pins[] = { 2193 /* SCL, SDA */ 2194 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 2195}; 2196 2197static const unsigned int i2c1_d_mux[] = { 2198 SCL1_D_MARK, SDA1_D_MARK, 2199}; 2200 2201static const unsigned int i2c2_a_pins[] = { 2202 /* SCL, SDA */ 2203 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), 2204}; 2205 2206static const unsigned int i2c2_a_mux[] = { 2207 SCL2_A_MARK, SDA2_A_MARK, 2208}; 2209 2210static const unsigned int i2c2_b_pins[] = { 2211 /* SCL, SDA */ 2212 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 2213}; 2214 2215static const unsigned int i2c2_b_mux[] = { 2216 SCL2_B_MARK, SDA2_B_MARK, 2217}; 2218 2219static const unsigned int i2c2_c_pins[] = { 2220 /* SCL, SDA */ 2221 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 2222}; 2223 2224static const unsigned int i2c2_c_mux[] = { 2225 SCL2_C_MARK, SDA2_C_MARK, 2226}; 2227 2228static const unsigned int i2c2_d_pins[] = { 2229 /* SCL, SDA */ 2230 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 2231}; 2232 2233static const unsigned int i2c2_d_mux[] = { 2234 SCL2_D_MARK, SDA2_D_MARK, 2235}; 2236 2237static const unsigned int i2c2_e_pins[] = { 2238 /* SCL, SDA */ 2239 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), 2240}; 2241 2242static const unsigned int i2c2_e_mux[] = { 2243 SCL2_E_MARK, SDA2_E_MARK, 2244}; 2245 2246static const unsigned int i2c4_pins[] = { 2247 /* SCL, SDA */ 2248 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 2249}; 2250 2251static const unsigned int i2c4_mux[] = { 2252 SCL4_MARK, SDA4_MARK, 2253}; 2254 2255static const unsigned int i2c5_pins[] = { 2256 /* SCL, SDA */ 2257 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 2258}; 2259 2260static const unsigned int i2c5_mux[] = { 2261 SCL5_MARK, SDA5_MARK, 2262}; 2263 2264static const unsigned int i2c6_a_pins[] = { 2265 /* SCL, SDA */ 2266 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 2267}; 2268 2269static const unsigned int i2c6_a_mux[] = { 2270 SCL6_A_MARK, SDA6_A_MARK, 2271}; 2272 2273static const unsigned int i2c6_b_pins[] = { 2274 /* SCL, SDA */ 2275 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 2276}; 2277 2278static const unsigned int i2c6_b_mux[] = { 2279 SCL6_B_MARK, SDA6_B_MARK, 2280}; 2281 2282static const unsigned int i2c7_a_pins[] = { 2283 /* SCL, SDA */ 2284 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), 2285}; 2286 2287static const unsigned int i2c7_a_mux[] = { 2288 SCL7_A_MARK, SDA7_A_MARK, 2289}; 2290 2291static const unsigned int i2c7_b_pins[] = { 2292 /* SCL, SDA */ 2293 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 2294}; 2295 2296static const unsigned int i2c7_b_mux[] = { 2297 SCL7_B_MARK, SDA7_B_MARK, 2298}; 2299 2300/* - INTC-EX ---------------------------------------------------------------- */ 2301static const unsigned int intc_ex_irq0_pins[] = { 2302 /* IRQ0 */ 2303 RCAR_GP_PIN(1, 0), 2304}; 2305static const unsigned int intc_ex_irq0_mux[] = { 2306 IRQ0_MARK, 2307}; 2308static const unsigned int intc_ex_irq1_pins[] = { 2309 /* IRQ1 */ 2310 RCAR_GP_PIN(1, 1), 2311}; 2312static const unsigned int intc_ex_irq1_mux[] = { 2313 IRQ1_MARK, 2314}; 2315static const unsigned int intc_ex_irq2_pins[] = { 2316 /* IRQ2 */ 2317 RCAR_GP_PIN(1, 2), 2318}; 2319static const unsigned int intc_ex_irq2_mux[] = { 2320 IRQ2_MARK, 2321}; 2322static const unsigned int intc_ex_irq3_pins[] = { 2323 /* IRQ3 */ 2324 RCAR_GP_PIN(1, 9), 2325}; 2326static const unsigned int intc_ex_irq3_mux[] = { 2327 IRQ3_MARK, 2328}; 2329static const unsigned int intc_ex_irq4_pins[] = { 2330 /* IRQ4 */ 2331 RCAR_GP_PIN(1, 10), 2332}; 2333static const unsigned int intc_ex_irq4_mux[] = { 2334 IRQ4_MARK, 2335}; 2336static const unsigned int intc_ex_irq5_pins[] = { 2337 /* IRQ5 */ 2338 RCAR_GP_PIN(0, 7), 2339}; 2340static const unsigned int intc_ex_irq5_mux[] = { 2341 IRQ5_MARK, 2342}; 2343 2344#ifdef CONFIG_PINCTRL_PFC_R8A77990 2345/* - MLB+ ------------------------------------------------------------------- */ 2346static const unsigned int mlb_3pin_pins[] = { 2347 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 2348}; 2349static const unsigned int mlb_3pin_mux[] = { 2350 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2351}; 2352#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 2353 2354/* - MSIOF0 ----------------------------------------------------------------- */ 2355static const unsigned int msiof0_clk_pins[] = { 2356 /* SCK */ 2357 RCAR_GP_PIN(5, 10), 2358}; 2359 2360static const unsigned int msiof0_clk_mux[] = { 2361 MSIOF0_SCK_MARK, 2362}; 2363 2364static const unsigned int msiof0_sync_pins[] = { 2365 /* SYNC */ 2366 RCAR_GP_PIN(5, 13), 2367}; 2368 2369static const unsigned int msiof0_sync_mux[] = { 2370 MSIOF0_SYNC_MARK, 2371}; 2372 2373static const unsigned int msiof0_ss1_pins[] = { 2374 /* SS1 */ 2375 RCAR_GP_PIN(5, 14), 2376}; 2377 2378static const unsigned int msiof0_ss1_mux[] = { 2379 MSIOF0_SS1_MARK, 2380}; 2381 2382static const unsigned int msiof0_ss2_pins[] = { 2383 /* SS2 */ 2384 RCAR_GP_PIN(5, 15), 2385}; 2386 2387static const unsigned int msiof0_ss2_mux[] = { 2388 MSIOF0_SS2_MARK, 2389}; 2390 2391static const unsigned int msiof0_txd_pins[] = { 2392 /* TXD */ 2393 RCAR_GP_PIN(5, 12), 2394}; 2395 2396static const unsigned int msiof0_txd_mux[] = { 2397 MSIOF0_TXD_MARK, 2398}; 2399 2400static const unsigned int msiof0_rxd_pins[] = { 2401 /* RXD */ 2402 RCAR_GP_PIN(5, 11), 2403}; 2404 2405static const unsigned int msiof0_rxd_mux[] = { 2406 MSIOF0_RXD_MARK, 2407}; 2408 2409/* - MSIOF1 ----------------------------------------------------------------- */ 2410static const unsigned int msiof1_clk_pins[] = { 2411 /* SCK */ 2412 RCAR_GP_PIN(1, 19), 2413}; 2414 2415static const unsigned int msiof1_clk_mux[] = { 2416 MSIOF1_SCK_MARK, 2417}; 2418 2419static const unsigned int msiof1_sync_pins[] = { 2420 /* SYNC */ 2421 RCAR_GP_PIN(1, 16), 2422}; 2423 2424static const unsigned int msiof1_sync_mux[] = { 2425 MSIOF1_SYNC_MARK, 2426}; 2427 2428static const unsigned int msiof1_ss1_pins[] = { 2429 /* SS1 */ 2430 RCAR_GP_PIN(1, 14), 2431}; 2432 2433static const unsigned int msiof1_ss1_mux[] = { 2434 MSIOF1_SS1_MARK, 2435}; 2436 2437static const unsigned int msiof1_ss2_pins[] = { 2438 /* SS2 */ 2439 RCAR_GP_PIN(1, 15), 2440}; 2441 2442static const unsigned int msiof1_ss2_mux[] = { 2443 MSIOF1_SS2_MARK, 2444}; 2445 2446static const unsigned int msiof1_txd_pins[] = { 2447 /* TXD */ 2448 RCAR_GP_PIN(1, 18), 2449}; 2450 2451static const unsigned int msiof1_txd_mux[] = { 2452 MSIOF1_TXD_MARK, 2453}; 2454 2455static const unsigned int msiof1_rxd_pins[] = { 2456 /* RXD */ 2457 RCAR_GP_PIN(1, 17), 2458}; 2459 2460static const unsigned int msiof1_rxd_mux[] = { 2461 MSIOF1_RXD_MARK, 2462}; 2463 2464/* - MSIOF2 ----------------------------------------------------------------- */ 2465static const unsigned int msiof2_clk_a_pins[] = { 2466 /* SCK */ 2467 RCAR_GP_PIN(0, 8), 2468}; 2469 2470static const unsigned int msiof2_clk_a_mux[] = { 2471 MSIOF2_SCK_A_MARK, 2472}; 2473 2474static const unsigned int msiof2_sync_a_pins[] = { 2475 /* SYNC */ 2476 RCAR_GP_PIN(0, 9), 2477}; 2478 2479static const unsigned int msiof2_sync_a_mux[] = { 2480 MSIOF2_SYNC_A_MARK, 2481}; 2482 2483static const unsigned int msiof2_ss1_a_pins[] = { 2484 /* SS1 */ 2485 RCAR_GP_PIN(0, 15), 2486}; 2487 2488static const unsigned int msiof2_ss1_a_mux[] = { 2489 MSIOF2_SS1_A_MARK, 2490}; 2491 2492static const unsigned int msiof2_ss2_a_pins[] = { 2493 /* SS2 */ 2494 RCAR_GP_PIN(0, 14), 2495}; 2496 2497static const unsigned int msiof2_ss2_a_mux[] = { 2498 MSIOF2_SS2_A_MARK, 2499}; 2500 2501static const unsigned int msiof2_txd_a_pins[] = { 2502 /* TXD */ 2503 RCAR_GP_PIN(0, 11), 2504}; 2505 2506static const unsigned int msiof2_txd_a_mux[] = { 2507 MSIOF2_TXD_A_MARK, 2508}; 2509 2510static const unsigned int msiof2_rxd_a_pins[] = { 2511 /* RXD */ 2512 RCAR_GP_PIN(0, 10), 2513}; 2514 2515static const unsigned int msiof2_rxd_a_mux[] = { 2516 MSIOF2_RXD_A_MARK, 2517}; 2518 2519static const unsigned int msiof2_clk_b_pins[] = { 2520 /* SCK */ 2521 RCAR_GP_PIN(1, 13), 2522}; 2523 2524static const unsigned int msiof2_clk_b_mux[] = { 2525 MSIOF2_SCK_B_MARK, 2526}; 2527 2528static const unsigned int msiof2_sync_b_pins[] = { 2529 /* SYNC */ 2530 RCAR_GP_PIN(1, 10), 2531}; 2532 2533static const unsigned int msiof2_sync_b_mux[] = { 2534 MSIOF2_SYNC_B_MARK, 2535}; 2536 2537static const unsigned int msiof2_ss1_b_pins[] = { 2538 /* SS1 */ 2539 RCAR_GP_PIN(1, 16), 2540}; 2541 2542static const unsigned int msiof2_ss1_b_mux[] = { 2543 MSIOF2_SS1_B_MARK, 2544}; 2545 2546static const unsigned int msiof2_ss2_b_pins[] = { 2547 /* SS2 */ 2548 RCAR_GP_PIN(1, 12), 2549}; 2550 2551static const unsigned int msiof2_ss2_b_mux[] = { 2552 MSIOF2_SS2_B_MARK, 2553}; 2554 2555static const unsigned int msiof2_txd_b_pins[] = { 2556 /* TXD */ 2557 RCAR_GP_PIN(1, 15), 2558}; 2559 2560static const unsigned int msiof2_txd_b_mux[] = { 2561 MSIOF2_TXD_B_MARK, 2562}; 2563 2564static const unsigned int msiof2_rxd_b_pins[] = { 2565 /* RXD */ 2566 RCAR_GP_PIN(1, 14), 2567}; 2568 2569static const unsigned int msiof2_rxd_b_mux[] = { 2570 MSIOF2_RXD_B_MARK, 2571}; 2572 2573/* - MSIOF3 ----------------------------------------------------------------- */ 2574static const unsigned int msiof3_clk_a_pins[] = { 2575 /* SCK */ 2576 RCAR_GP_PIN(0, 0), 2577}; 2578 2579static const unsigned int msiof3_clk_a_mux[] = { 2580 MSIOF3_SCK_A_MARK, 2581}; 2582 2583static const unsigned int msiof3_sync_a_pins[] = { 2584 /* SYNC */ 2585 RCAR_GP_PIN(0, 1), 2586}; 2587 2588static const unsigned int msiof3_sync_a_mux[] = { 2589 MSIOF3_SYNC_A_MARK, 2590}; 2591 2592static const unsigned int msiof3_ss1_a_pins[] = { 2593 /* SS1 */ 2594 RCAR_GP_PIN(0, 15), 2595}; 2596 2597static const unsigned int msiof3_ss1_a_mux[] = { 2598 MSIOF3_SS1_A_MARK, 2599}; 2600 2601static const unsigned int msiof3_ss2_a_pins[] = { 2602 /* SS2 */ 2603 RCAR_GP_PIN(0, 4), 2604}; 2605 2606static const unsigned int msiof3_ss2_a_mux[] = { 2607 MSIOF3_SS2_A_MARK, 2608}; 2609 2610static const unsigned int msiof3_txd_a_pins[] = { 2611 /* TXD */ 2612 RCAR_GP_PIN(0, 3), 2613}; 2614 2615static const unsigned int msiof3_txd_a_mux[] = { 2616 MSIOF3_TXD_A_MARK, 2617}; 2618 2619static const unsigned int msiof3_rxd_a_pins[] = { 2620 /* RXD */ 2621 RCAR_GP_PIN(0, 2), 2622}; 2623 2624static const unsigned int msiof3_rxd_a_mux[] = { 2625 MSIOF3_RXD_A_MARK, 2626}; 2627 2628static const unsigned int msiof3_clk_b_pins[] = { 2629 /* SCK */ 2630 RCAR_GP_PIN(1, 5), 2631}; 2632 2633static const unsigned int msiof3_clk_b_mux[] = { 2634 MSIOF3_SCK_B_MARK, 2635}; 2636 2637static const unsigned int msiof3_sync_b_pins[] = { 2638 /* SYNC */ 2639 RCAR_GP_PIN(1, 4), 2640}; 2641 2642static const unsigned int msiof3_sync_b_mux[] = { 2643 MSIOF3_SYNC_B_MARK, 2644}; 2645 2646static const unsigned int msiof3_ss1_b_pins[] = { 2647 /* SS1 */ 2648 RCAR_GP_PIN(1, 0), 2649}; 2650 2651static const unsigned int msiof3_ss1_b_mux[] = { 2652 MSIOF3_SS1_B_MARK, 2653}; 2654 2655static const unsigned int msiof3_txd_b_pins[] = { 2656 /* TXD */ 2657 RCAR_GP_PIN(1, 7), 2658}; 2659 2660static const unsigned int msiof3_txd_b_mux[] = { 2661 MSIOF3_TXD_B_MARK, 2662}; 2663 2664static const unsigned int msiof3_rxd_b_pins[] = { 2665 /* RXD */ 2666 RCAR_GP_PIN(1, 6), 2667}; 2668 2669static const unsigned int msiof3_rxd_b_mux[] = { 2670 MSIOF3_RXD_B_MARK, 2671}; 2672 2673/* - PWM0 --------------------------------------------------------------------*/ 2674static const unsigned int pwm0_a_pins[] = { 2675 /* PWM */ 2676 RCAR_GP_PIN(2, 22), 2677}; 2678 2679static const unsigned int pwm0_a_mux[] = { 2680 PWM0_A_MARK, 2681}; 2682 2683static const unsigned int pwm0_b_pins[] = { 2684 /* PWM */ 2685 RCAR_GP_PIN(6, 3), 2686}; 2687 2688static const unsigned int pwm0_b_mux[] = { 2689 PWM0_B_MARK, 2690}; 2691 2692/* - PWM1 --------------------------------------------------------------------*/ 2693static const unsigned int pwm1_a_pins[] = { 2694 /* PWM */ 2695 RCAR_GP_PIN(2, 23), 2696}; 2697 2698static const unsigned int pwm1_a_mux[] = { 2699 PWM1_A_MARK, 2700}; 2701 2702static const unsigned int pwm1_b_pins[] = { 2703 /* PWM */ 2704 RCAR_GP_PIN(6, 4), 2705}; 2706 2707static const unsigned int pwm1_b_mux[] = { 2708 PWM1_B_MARK, 2709}; 2710 2711/* - PWM2 --------------------------------------------------------------------*/ 2712static const unsigned int pwm2_a_pins[] = { 2713 /* PWM */ 2714 RCAR_GP_PIN(1, 0), 2715}; 2716 2717static const unsigned int pwm2_a_mux[] = { 2718 PWM2_A_MARK, 2719}; 2720 2721static const unsigned int pwm2_b_pins[] = { 2722 /* PWM */ 2723 RCAR_GP_PIN(1, 4), 2724}; 2725 2726static const unsigned int pwm2_b_mux[] = { 2727 PWM2_B_MARK, 2728}; 2729 2730static const unsigned int pwm2_c_pins[] = { 2731 /* PWM */ 2732 RCAR_GP_PIN(6, 5), 2733}; 2734 2735static const unsigned int pwm2_c_mux[] = { 2736 PWM2_C_MARK, 2737}; 2738 2739/* - PWM3 --------------------------------------------------------------------*/ 2740static const unsigned int pwm3_a_pins[] = { 2741 /* PWM */ 2742 RCAR_GP_PIN(1, 1), 2743}; 2744 2745static const unsigned int pwm3_a_mux[] = { 2746 PWM3_A_MARK, 2747}; 2748 2749static const unsigned int pwm3_b_pins[] = { 2750 /* PWM */ 2751 RCAR_GP_PIN(1, 5), 2752}; 2753 2754static const unsigned int pwm3_b_mux[] = { 2755 PWM3_B_MARK, 2756}; 2757 2758static const unsigned int pwm3_c_pins[] = { 2759 /* PWM */ 2760 RCAR_GP_PIN(6, 6), 2761}; 2762 2763static const unsigned int pwm3_c_mux[] = { 2764 PWM3_C_MARK, 2765}; 2766 2767/* - PWM4 --------------------------------------------------------------------*/ 2768static const unsigned int pwm4_a_pins[] = { 2769 /* PWM */ 2770 RCAR_GP_PIN(1, 3), 2771}; 2772 2773static const unsigned int pwm4_a_mux[] = { 2774 PWM4_A_MARK, 2775}; 2776 2777static const unsigned int pwm4_b_pins[] = { 2778 /* PWM */ 2779 RCAR_GP_PIN(6, 7), 2780}; 2781 2782static const unsigned int pwm4_b_mux[] = { 2783 PWM4_B_MARK, 2784}; 2785 2786/* - PWM5 --------------------------------------------------------------------*/ 2787static const unsigned int pwm5_a_pins[] = { 2788 /* PWM */ 2789 RCAR_GP_PIN(2, 24), 2790}; 2791 2792static const unsigned int pwm5_a_mux[] = { 2793 PWM5_A_MARK, 2794}; 2795 2796static const unsigned int pwm5_b_pins[] = { 2797 /* PWM */ 2798 RCAR_GP_PIN(6, 10), 2799}; 2800 2801static const unsigned int pwm5_b_mux[] = { 2802 PWM5_B_MARK, 2803}; 2804 2805/* - PWM6 --------------------------------------------------------------------*/ 2806static const unsigned int pwm6_a_pins[] = { 2807 /* PWM */ 2808 RCAR_GP_PIN(2, 25), 2809}; 2810 2811static const unsigned int pwm6_a_mux[] = { 2812 PWM6_A_MARK, 2813}; 2814 2815static const unsigned int pwm6_b_pins[] = { 2816 /* PWM */ 2817 RCAR_GP_PIN(6, 11), 2818}; 2819 2820static const unsigned int pwm6_b_mux[] = { 2821 PWM6_B_MARK, 2822}; 2823 2824/* - QSPI0 ------------------------------------------------------------------ */ 2825static const unsigned int qspi0_ctrl_pins[] = { 2826 /* QSPI0_SPCLK, QSPI0_SSL */ 2827 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5), 2828}; 2829static const unsigned int qspi0_ctrl_mux[] = { 2830 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2831}; 2832/* - QSPI1 ------------------------------------------------------------------ */ 2833static const unsigned int qspi1_ctrl_pins[] = { 2834 /* QSPI1_SPCLK, QSPI1_SSL */ 2835 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11), 2836}; 2837static const unsigned int qspi1_ctrl_mux[] = { 2838 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2839}; 2840 2841/* - RPC -------------------------------------------------------------------- */ 2842static const unsigned int rpc_clk_pins[] = { 2843 /* Octal-SPI flash: C/SCLK */ 2844 /* HyperFlash: CK, CK# */ 2845 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6), 2846}; 2847static const unsigned int rpc_clk_mux[] = { 2848 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 2849}; 2850static const unsigned int rpc_ctrl_pins[] = { 2851 /* Octal-SPI flash: S#/CS, DQS */ 2852 /* HyperFlash: CS#, RDS */ 2853 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11), 2854}; 2855static const unsigned int rpc_ctrl_mux[] = { 2856 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 2857}; 2858static const unsigned int rpc_data_pins[] = { 2859 /* DQ[0:7] */ 2860 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 2861 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 2862 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2863 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 2864}; 2865static const unsigned int rpc_data_mux[] = { 2866 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2867 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 2868 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2869 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 2870}; 2871static const unsigned int rpc_reset_pins[] = { 2872 /* RPC_RESET# */ 2873 RCAR_GP_PIN(2, 13), 2874}; 2875static const unsigned int rpc_reset_mux[] = { 2876 RPC_RESET_N_MARK, 2877}; 2878static const unsigned int rpc_int_pins[] = { 2879 /* RPC_INT# */ 2880 RCAR_GP_PIN(2, 12), 2881}; 2882static const unsigned int rpc_int_mux[] = { 2883 RPC_INT_N_MARK, 2884}; 2885 2886/* - SCIF0 ------------------------------------------------------------------ */ 2887static const unsigned int scif0_data_a_pins[] = { 2888 /* RX, TX */ 2889 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2890}; 2891 2892static const unsigned int scif0_data_a_mux[] = { 2893 RX0_A_MARK, TX0_A_MARK, 2894}; 2895 2896static const unsigned int scif0_clk_a_pins[] = { 2897 /* SCK */ 2898 RCAR_GP_PIN(5, 0), 2899}; 2900 2901static const unsigned int scif0_clk_a_mux[] = { 2902 SCK0_A_MARK, 2903}; 2904 2905static const unsigned int scif0_ctrl_a_pins[] = { 2906 /* RTS, CTS */ 2907 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2908}; 2909 2910static const unsigned int scif0_ctrl_a_mux[] = { 2911 RTS0_N_A_MARK, CTS0_N_A_MARK, 2912}; 2913 2914static const unsigned int scif0_data_b_pins[] = { 2915 /* RX, TX */ 2916 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), 2917}; 2918 2919static const unsigned int scif0_data_b_mux[] = { 2920 RX0_B_MARK, TX0_B_MARK, 2921}; 2922 2923static const unsigned int scif0_clk_b_pins[] = { 2924 /* SCK */ 2925 RCAR_GP_PIN(5, 18), 2926}; 2927 2928static const unsigned int scif0_clk_b_mux[] = { 2929 SCK0_B_MARK, 2930}; 2931 2932/* - SCIF1 ------------------------------------------------------------------ */ 2933static const unsigned int scif1_data_pins[] = { 2934 /* RX, TX */ 2935 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2936}; 2937 2938static const unsigned int scif1_data_mux[] = { 2939 RX1_MARK, TX1_MARK, 2940}; 2941 2942static const unsigned int scif1_clk_pins[] = { 2943 /* SCK */ 2944 RCAR_GP_PIN(5, 16), 2945}; 2946 2947static const unsigned int scif1_clk_mux[] = { 2948 SCK1_MARK, 2949}; 2950 2951static const unsigned int scif1_ctrl_pins[] = { 2952 /* RTS, CTS */ 2953 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), 2954}; 2955 2956static const unsigned int scif1_ctrl_mux[] = { 2957 RTS1_N_MARK, CTS1_N_MARK, 2958}; 2959 2960/* - SCIF2 ------------------------------------------------------------------ */ 2961static const unsigned int scif2_data_a_pins[] = { 2962 /* RX, TX */ 2963 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 2964}; 2965 2966static const unsigned int scif2_data_a_mux[] = { 2967 RX2_A_MARK, TX2_A_MARK, 2968}; 2969 2970static const unsigned int scif2_clk_a_pins[] = { 2971 /* SCK */ 2972 RCAR_GP_PIN(5, 7), 2973}; 2974 2975static const unsigned int scif2_clk_a_mux[] = { 2976 SCK2_A_MARK, 2977}; 2978 2979static const unsigned int scif2_data_b_pins[] = { 2980 /* RX, TX */ 2981 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 2982}; 2983 2984static const unsigned int scif2_data_b_mux[] = { 2985 RX2_B_MARK, TX2_B_MARK, 2986}; 2987 2988/* - SCIF3 ------------------------------------------------------------------ */ 2989static const unsigned int scif3_data_a_pins[] = { 2990 /* RX, TX */ 2991 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2992}; 2993 2994static const unsigned int scif3_data_a_mux[] = { 2995 RX3_A_MARK, TX3_A_MARK, 2996}; 2997 2998static const unsigned int scif3_clk_a_pins[] = { 2999 /* SCK */ 3000 RCAR_GP_PIN(0, 1), 3001}; 3002 3003static const unsigned int scif3_clk_a_mux[] = { 3004 SCK3_A_MARK, 3005}; 3006 3007static const unsigned int scif3_ctrl_a_pins[] = { 3008 /* RTS, CTS */ 3009 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 3010}; 3011 3012static const unsigned int scif3_ctrl_a_mux[] = { 3013 RTS3_N_A_MARK, CTS3_N_A_MARK, 3014}; 3015 3016static const unsigned int scif3_data_b_pins[] = { 3017 /* RX, TX */ 3018 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3019}; 3020 3021static const unsigned int scif3_data_b_mux[] = { 3022 RX3_B_MARK, TX3_B_MARK, 3023}; 3024 3025static const unsigned int scif3_data_c_pins[] = { 3026 /* RX, TX */ 3027 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3028}; 3029 3030static const unsigned int scif3_data_c_mux[] = { 3031 RX3_C_MARK, TX3_C_MARK, 3032}; 3033 3034static const unsigned int scif3_clk_c_pins[] = { 3035 /* SCK */ 3036 RCAR_GP_PIN(2, 24), 3037}; 3038 3039static const unsigned int scif3_clk_c_mux[] = { 3040 SCK3_C_MARK, 3041}; 3042 3043/* - SCIF4 ------------------------------------------------------------------ */ 3044static const unsigned int scif4_data_a_pins[] = { 3045 /* RX, TX */ 3046 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3047}; 3048 3049static const unsigned int scif4_data_a_mux[] = { 3050 RX4_A_MARK, TX4_A_MARK, 3051}; 3052 3053static const unsigned int scif4_clk_a_pins[] = { 3054 /* SCK */ 3055 RCAR_GP_PIN(1, 5), 3056}; 3057 3058static const unsigned int scif4_clk_a_mux[] = { 3059 SCK4_A_MARK, 3060}; 3061 3062static const unsigned int scif4_ctrl_a_pins[] = { 3063 /* RTS, CTS */ 3064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), 3065}; 3066 3067static const unsigned int scif4_ctrl_a_mux[] = { 3068 RTS4_N_A_MARK, CTS4_N_A_MARK, 3069}; 3070 3071static const unsigned int scif4_data_b_pins[] = { 3072 /* RX, TX */ 3073 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 3074}; 3075 3076static const unsigned int scif4_data_b_mux[] = { 3077 RX4_B_MARK, TX4_B_MARK, 3078}; 3079 3080static const unsigned int scif4_clk_b_pins[] = { 3081 /* SCK */ 3082 RCAR_GP_PIN(0, 8), 3083}; 3084 3085static const unsigned int scif4_clk_b_mux[] = { 3086 SCK4_B_MARK, 3087}; 3088 3089static const unsigned int scif4_data_c_pins[] = { 3090 /* RX, TX */ 3091 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3092}; 3093 3094static const unsigned int scif4_data_c_mux[] = { 3095 RX4_C_MARK, TX4_C_MARK, 3096}; 3097 3098static const unsigned int scif4_ctrl_c_pins[] = { 3099 /* RTS, CTS */ 3100 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 3101}; 3102 3103static const unsigned int scif4_ctrl_c_mux[] = { 3104 RTS4_N_C_MARK, CTS4_N_C_MARK, 3105}; 3106 3107/* - SCIF5 ------------------------------------------------------------------ */ 3108static const unsigned int scif5_data_a_pins[] = { 3109 /* RX, TX */ 3110 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), 3111}; 3112 3113static const unsigned int scif5_data_a_mux[] = { 3114 RX5_A_MARK, TX5_A_MARK, 3115}; 3116 3117static const unsigned int scif5_clk_a_pins[] = { 3118 /* SCK */ 3119 RCAR_GP_PIN(1, 13), 3120}; 3121 3122static const unsigned int scif5_clk_a_mux[] = { 3123 SCK5_A_MARK, 3124}; 3125 3126static const unsigned int scif5_data_b_pins[] = { 3127 /* RX, TX */ 3128 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3129}; 3130 3131static const unsigned int scif5_data_b_mux[] = { 3132 RX5_B_MARK, TX5_B_MARK, 3133}; 3134 3135static const unsigned int scif5_data_c_pins[] = { 3136 /* RX, TX */ 3137 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3138}; 3139 3140static const unsigned int scif5_data_c_mux[] = { 3141 RX5_C_MARK, TX5_C_MARK, 3142}; 3143 3144/* - SCIF Clock ------------------------------------------------------------- */ 3145static const unsigned int scif_clk_a_pins[] = { 3146 /* SCIF_CLK */ 3147 RCAR_GP_PIN(5, 3), 3148}; 3149 3150static const unsigned int scif_clk_a_mux[] = { 3151 SCIF_CLK_A_MARK, 3152}; 3153 3154static const unsigned int scif_clk_b_pins[] = { 3155 /* SCIF_CLK */ 3156 RCAR_GP_PIN(5, 7), 3157}; 3158 3159static const unsigned int scif_clk_b_mux[] = { 3160 SCIF_CLK_B_MARK, 3161}; 3162 3163/* - SDHI0 ------------------------------------------------------------------ */ 3164static const unsigned int sdhi0_data_pins[] = { 3165 /* D[0:3] */ 3166 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3167 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3168}; 3169 3170static const unsigned int sdhi0_data_mux[] = { 3171 SD0_DAT0_MARK, SD0_DAT1_MARK, 3172 SD0_DAT2_MARK, SD0_DAT3_MARK, 3173}; 3174 3175static const unsigned int sdhi0_ctrl_pins[] = { 3176 /* CLK, CMD */ 3177 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3178}; 3179 3180static const unsigned int sdhi0_ctrl_mux[] = { 3181 SD0_CLK_MARK, SD0_CMD_MARK, 3182}; 3183 3184static const unsigned int sdhi0_cd_pins[] = { 3185 /* CD */ 3186 RCAR_GP_PIN(3, 12), 3187}; 3188 3189static const unsigned int sdhi0_cd_mux[] = { 3190 SD0_CD_MARK, 3191}; 3192 3193static const unsigned int sdhi0_wp_pins[] = { 3194 /* WP */ 3195 RCAR_GP_PIN(3, 13), 3196}; 3197 3198static const unsigned int sdhi0_wp_mux[] = { 3199 SD0_WP_MARK, 3200}; 3201 3202/* - SDHI1 ------------------------------------------------------------------ */ 3203static const unsigned int sdhi1_data_pins[] = { 3204 /* D[0:3] */ 3205 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3206 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3207}; 3208 3209static const unsigned int sdhi1_data_mux[] = { 3210 SD1_DAT0_MARK, SD1_DAT1_MARK, 3211 SD1_DAT2_MARK, SD1_DAT3_MARK, 3212}; 3213 3214static const unsigned int sdhi1_ctrl_pins[] = { 3215 /* CLK, CMD */ 3216 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3217}; 3218 3219static const unsigned int sdhi1_ctrl_mux[] = { 3220 SD1_CLK_MARK, SD1_CMD_MARK, 3221}; 3222 3223static const unsigned int sdhi1_cd_pins[] = { 3224 /* CD */ 3225 RCAR_GP_PIN(3, 14), 3226}; 3227 3228static const unsigned int sdhi1_cd_mux[] = { 3229 SD1_CD_MARK, 3230}; 3231 3232static const unsigned int sdhi1_wp_pins[] = { 3233 /* WP */ 3234 RCAR_GP_PIN(3, 15), 3235}; 3236 3237static const unsigned int sdhi1_wp_mux[] = { 3238 SD1_WP_MARK, 3239}; 3240 3241/* - SDHI3 ------------------------------------------------------------------ */ 3242static const unsigned int sdhi3_data_pins[] = { 3243 /* D[0:7] */ 3244 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3245 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3246 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 3247 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3248}; 3249 3250static const unsigned int sdhi3_data_mux[] = { 3251 SD3_DAT0_MARK, SD3_DAT1_MARK, 3252 SD3_DAT2_MARK, SD3_DAT3_MARK, 3253 SD3_DAT4_MARK, SD3_DAT5_MARK, 3254 SD3_DAT6_MARK, SD3_DAT7_MARK, 3255}; 3256 3257static const unsigned int sdhi3_ctrl_pins[] = { 3258 /* CLK, CMD */ 3259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3260}; 3261 3262static const unsigned int sdhi3_ctrl_mux[] = { 3263 SD3_CLK_MARK, SD3_CMD_MARK, 3264}; 3265 3266static const unsigned int sdhi3_cd_pins[] = { 3267 /* CD */ 3268 RCAR_GP_PIN(3, 12), 3269}; 3270 3271static const unsigned int sdhi3_cd_mux[] = { 3272 SD3_CD_MARK, 3273}; 3274 3275static const unsigned int sdhi3_wp_pins[] = { 3276 /* WP */ 3277 RCAR_GP_PIN(3, 13), 3278}; 3279 3280static const unsigned int sdhi3_wp_mux[] = { 3281 SD3_WP_MARK, 3282}; 3283 3284static const unsigned int sdhi3_ds_pins[] = { 3285 /* DS */ 3286 RCAR_GP_PIN(4, 10), 3287}; 3288 3289static const unsigned int sdhi3_ds_mux[] = { 3290 SD3_DS_MARK, 3291}; 3292 3293/* - SSI -------------------------------------------------------------------- */ 3294static const unsigned int ssi0_data_pins[] = { 3295 /* SDATA */ 3296 RCAR_GP_PIN(6, 2), 3297}; 3298 3299static const unsigned int ssi0_data_mux[] = { 3300 SSI_SDATA0_MARK, 3301}; 3302 3303static const unsigned int ssi01239_ctrl_pins[] = { 3304 /* SCK, WS */ 3305 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3306}; 3307 3308static const unsigned int ssi01239_ctrl_mux[] = { 3309 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3310}; 3311 3312static const unsigned int ssi1_data_pins[] = { 3313 /* SDATA */ 3314 RCAR_GP_PIN(6, 3), 3315}; 3316 3317static const unsigned int ssi1_data_mux[] = { 3318 SSI_SDATA1_MARK, 3319}; 3320 3321static const unsigned int ssi1_ctrl_pins[] = { 3322 /* SCK, WS */ 3323 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 3324}; 3325 3326static const unsigned int ssi1_ctrl_mux[] = { 3327 SSI_SCK1_MARK, SSI_WS1_MARK, 3328}; 3329 3330static const unsigned int ssi2_data_pins[] = { 3331 /* SDATA */ 3332 RCAR_GP_PIN(6, 4), 3333}; 3334 3335static const unsigned int ssi2_data_mux[] = { 3336 SSI_SDATA2_MARK, 3337}; 3338 3339static const unsigned int ssi2_ctrl_a_pins[] = { 3340 /* SCK, WS */ 3341 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3342}; 3343 3344static const unsigned int ssi2_ctrl_a_mux[] = { 3345 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3346}; 3347 3348static const unsigned int ssi2_ctrl_b_pins[] = { 3349 /* SCK, WS */ 3350 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3351}; 3352 3353static const unsigned int ssi2_ctrl_b_mux[] = { 3354 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3355}; 3356 3357static const unsigned int ssi3_data_pins[] = { 3358 /* SDATA */ 3359 RCAR_GP_PIN(6, 7), 3360}; 3361 3362static const unsigned int ssi3_data_mux[] = { 3363 SSI_SDATA3_MARK, 3364}; 3365 3366static const unsigned int ssi349_ctrl_pins[] = { 3367 /* SCK, WS */ 3368 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3369}; 3370 3371static const unsigned int ssi349_ctrl_mux[] = { 3372 SSI_SCK349_MARK, SSI_WS349_MARK, 3373}; 3374 3375static const unsigned int ssi4_data_pins[] = { 3376 /* SDATA */ 3377 RCAR_GP_PIN(6, 10), 3378}; 3379 3380static const unsigned int ssi4_data_mux[] = { 3381 SSI_SDATA4_MARK, 3382}; 3383 3384static const unsigned int ssi4_ctrl_pins[] = { 3385 /* SCK, WS */ 3386 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3387}; 3388 3389static const unsigned int ssi4_ctrl_mux[] = { 3390 SSI_SCK4_MARK, SSI_WS4_MARK, 3391}; 3392 3393static const unsigned int ssi5_data_pins[] = { 3394 /* SDATA */ 3395 RCAR_GP_PIN(6, 13), 3396}; 3397 3398static const unsigned int ssi5_data_mux[] = { 3399 SSI_SDATA5_MARK, 3400}; 3401 3402static const unsigned int ssi5_ctrl_pins[] = { 3403 /* SCK, WS */ 3404 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3405}; 3406 3407static const unsigned int ssi5_ctrl_mux[] = { 3408 SSI_SCK5_MARK, SSI_WS5_MARK, 3409}; 3410 3411static const unsigned int ssi6_data_pins[] = { 3412 /* SDATA */ 3413 RCAR_GP_PIN(6, 16), 3414}; 3415 3416static const unsigned int ssi6_data_mux[] = { 3417 SSI_SDATA6_MARK, 3418}; 3419 3420static const unsigned int ssi6_ctrl_pins[] = { 3421 /* SCK, WS */ 3422 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3423}; 3424 3425static const unsigned int ssi6_ctrl_mux[] = { 3426 SSI_SCK6_MARK, SSI_WS6_MARK, 3427}; 3428 3429static const unsigned int ssi7_data_pins[] = { 3430 /* SDATA */ 3431 RCAR_GP_PIN(5, 12), 3432}; 3433 3434static const unsigned int ssi7_data_mux[] = { 3435 SSI_SDATA7_MARK, 3436}; 3437 3438static const unsigned int ssi78_ctrl_pins[] = { 3439 /* SCK, WS */ 3440 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3441}; 3442 3443static const unsigned int ssi78_ctrl_mux[] = { 3444 SSI_SCK78_MARK, SSI_WS78_MARK, 3445}; 3446 3447static const unsigned int ssi8_data_pins[] = { 3448 /* SDATA */ 3449 RCAR_GP_PIN(5, 13), 3450}; 3451 3452static const unsigned int ssi8_data_mux[] = { 3453 SSI_SDATA8_MARK, 3454}; 3455 3456static const unsigned int ssi9_data_pins[] = { 3457 /* SDATA */ 3458 RCAR_GP_PIN(5, 16), 3459}; 3460 3461static const unsigned int ssi9_data_mux[] = { 3462 SSI_SDATA9_MARK, 3463}; 3464 3465static const unsigned int ssi9_ctrl_a_pins[] = { 3466 /* SCK, WS */ 3467 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), 3468}; 3469 3470static const unsigned int ssi9_ctrl_a_mux[] = { 3471 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3472}; 3473 3474static const unsigned int ssi9_ctrl_b_pins[] = { 3475 /* SCK, WS */ 3476 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3477}; 3478 3479static const unsigned int ssi9_ctrl_b_mux[] = { 3480 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3481}; 3482 3483/* - TMU -------------------------------------------------------------------- */ 3484static const unsigned int tmu_tclk1_a_pins[] = { 3485 /* TCLK */ 3486 RCAR_GP_PIN(3, 12), 3487}; 3488 3489static const unsigned int tmu_tclk1_a_mux[] = { 3490 TCLK1_A_MARK, 3491}; 3492 3493static const unsigned int tmu_tclk1_b_pins[] = { 3494 /* TCLK */ 3495 RCAR_GP_PIN(5, 17), 3496}; 3497 3498static const unsigned int tmu_tclk1_b_mux[] = { 3499 TCLK1_B_MARK, 3500}; 3501 3502static const unsigned int tmu_tclk2_a_pins[] = { 3503 /* TCLK */ 3504 RCAR_GP_PIN(3, 13), 3505}; 3506 3507static const unsigned int tmu_tclk2_a_mux[] = { 3508 TCLK2_A_MARK, 3509}; 3510 3511static const unsigned int tmu_tclk2_b_pins[] = { 3512 /* TCLK */ 3513 RCAR_GP_PIN(5, 18), 3514}; 3515 3516static const unsigned int tmu_tclk2_b_mux[] = { 3517 TCLK2_B_MARK, 3518}; 3519 3520/* - USB0 ------------------------------------------------------------------- */ 3521static const unsigned int usb0_a_pins[] = { 3522 /* PWEN, OVC */ 3523 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3524}; 3525 3526static const unsigned int usb0_a_mux[] = { 3527 USB0_PWEN_A_MARK, USB0_OVC_A_MARK, 3528}; 3529 3530static const unsigned int usb0_b_pins[] = { 3531 /* PWEN, OVC */ 3532 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3533}; 3534 3535static const unsigned int usb0_b_mux[] = { 3536 USB0_PWEN_B_MARK, USB0_OVC_B_MARK, 3537}; 3538 3539static const unsigned int usb0_id_pins[] = { 3540 /* ID */ 3541 RCAR_GP_PIN(5, 0) 3542}; 3543 3544static const unsigned int usb0_id_mux[] = { 3545 USB0_ID_MARK, 3546}; 3547 3548/* - USB30 ------------------------------------------------------------------ */ 3549static const unsigned int usb30_pins[] = { 3550 /* PWEN, OVC */ 3551 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3552}; 3553 3554static const unsigned int usb30_mux[] = { 3555 USB30_PWEN_MARK, USB30_OVC_MARK, 3556}; 3557 3558static const unsigned int usb30_id_pins[] = { 3559 /* ID */ 3560 RCAR_GP_PIN(5, 0), 3561}; 3562 3563static const unsigned int usb30_id_mux[] = { 3564 USB3HS0_ID_MARK, 3565}; 3566 3567/* - VIN4 ------------------------------------------------------------------- */ 3568static const unsigned int vin4_data18_a_pins[] = { 3569 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3570 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3571 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3572 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3573 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3574 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3575 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3576 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3577 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3578}; 3579 3580static const unsigned int vin4_data18_a_mux[] = { 3581 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3582 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3583 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3584 VI4_DATA10_MARK, VI4_DATA11_MARK, 3585 VI4_DATA12_MARK, VI4_DATA13_MARK, 3586 VI4_DATA14_MARK, VI4_DATA15_MARK, 3587 VI4_DATA18_MARK, VI4_DATA19_MARK, 3588 VI4_DATA20_MARK, VI4_DATA21_MARK, 3589 VI4_DATA22_MARK, VI4_DATA23_MARK, 3590}; 3591 3592static const unsigned int vin4_data_a_pins[] = { 3593 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3594 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3595 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3596 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3597 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3598 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3599 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3600 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3601 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3602 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3603 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3604 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3605}; 3606 3607static const unsigned int vin4_data_a_mux[] = { 3608 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 3609 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3610 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3611 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3612 VI4_DATA8_MARK, VI4_DATA9_MARK, 3613 VI4_DATA10_MARK, VI4_DATA11_MARK, 3614 VI4_DATA12_MARK, VI4_DATA13_MARK, 3615 VI4_DATA14_MARK, VI4_DATA15_MARK, 3616 VI4_DATA16_MARK, VI4_DATA17_MARK, 3617 VI4_DATA18_MARK, VI4_DATA19_MARK, 3618 VI4_DATA20_MARK, VI4_DATA21_MARK, 3619 VI4_DATA22_MARK, VI4_DATA23_MARK, 3620}; 3621 3622static const unsigned int vin4_data18_b_pins[] = { 3623 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3624 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3625 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3626 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3627 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3628 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3629 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3630 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3631 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3632}; 3633 3634static const unsigned int vin4_data18_b_mux[] = { 3635 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3636 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3637 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3638 VI4_DATA10_MARK, VI4_DATA11_MARK, 3639 VI4_DATA12_MARK, VI4_DATA13_MARK, 3640 VI4_DATA14_MARK, VI4_DATA15_MARK, 3641 VI4_DATA18_MARK, VI4_DATA19_MARK, 3642 VI4_DATA20_MARK, VI4_DATA21_MARK, 3643 VI4_DATA22_MARK, VI4_DATA23_MARK, 3644}; 3645 3646static const unsigned int vin4_data_b_pins[] = { 3647 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3648 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3649 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3650 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3651 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3652 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3653 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3654 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3655 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3656 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3657 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3658 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3659}; 3660 3661static const unsigned int vin4_data_b_mux[] = { 3662 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 3663 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3664 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3665 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3666 VI4_DATA8_MARK, VI4_DATA9_MARK, 3667 VI4_DATA10_MARK, VI4_DATA11_MARK, 3668 VI4_DATA12_MARK, VI4_DATA13_MARK, 3669 VI4_DATA14_MARK, VI4_DATA15_MARK, 3670 VI4_DATA16_MARK, VI4_DATA17_MARK, 3671 VI4_DATA18_MARK, VI4_DATA19_MARK, 3672 VI4_DATA20_MARK, VI4_DATA21_MARK, 3673 VI4_DATA22_MARK, VI4_DATA23_MARK, 3674}; 3675 3676static const unsigned int vin4_sync_pins[] = { 3677 /* HSYNC, VSYNC */ 3678 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3679}; 3680 3681static const unsigned int vin4_sync_mux[] = { 3682 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 3683}; 3684 3685static const unsigned int vin4_field_pins[] = { 3686 RCAR_GP_PIN(2, 23), 3687}; 3688 3689static const unsigned int vin4_field_mux[] = { 3690 VI4_FIELD_MARK, 3691}; 3692 3693static const unsigned int vin4_clkenb_pins[] = { 3694 RCAR_GP_PIN(1, 2), 3695}; 3696 3697static const unsigned int vin4_clkenb_mux[] = { 3698 VI4_CLKENB_MARK, 3699}; 3700 3701static const unsigned int vin4_clk_pins[] = { 3702 RCAR_GP_PIN(2, 22), 3703}; 3704 3705static const unsigned int vin4_clk_mux[] = { 3706 VI4_CLK_MARK, 3707}; 3708 3709/* - VIN5 ------------------------------------------------------------------- */ 3710static const unsigned int vin5_data_a_pins[] = { 3711 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 3712 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), 3713 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3714 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3715 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3716 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), 3717 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), 3718 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3719}; 3720 3721static const unsigned int vin5_data_a_mux[] = { 3722 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, 3723 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, 3724 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, 3725 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, 3726 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, 3727 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, 3728 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, 3729 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, 3730}; 3731 3732static const unsigned int vin5_data8_b_pins[] = { 3733 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), 3734 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), 3735 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 3736 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3737}; 3738 3739static const unsigned int vin5_data8_b_mux[] = { 3740 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, 3741 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, 3742 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, 3743 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, 3744}; 3745 3746static const unsigned int vin5_sync_a_pins[] = { 3747 /* HSYNC_N, VSYNC_N */ 3748 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), 3749}; 3750 3751static const unsigned int vin5_sync_a_mux[] = { 3752 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, 3753}; 3754 3755static const unsigned int vin5_field_a_pins[] = { 3756 RCAR_GP_PIN(1, 10), 3757}; 3758 3759static const unsigned int vin5_field_a_mux[] = { 3760 VI5_FIELD_A_MARK, 3761}; 3762 3763static const unsigned int vin5_clkenb_a_pins[] = { 3764 RCAR_GP_PIN(0, 1), 3765}; 3766 3767static const unsigned int vin5_clkenb_a_mux[] = { 3768 VI5_CLKENB_A_MARK, 3769}; 3770 3771static const unsigned int vin5_clk_a_pins[] = { 3772 RCAR_GP_PIN(1, 0), 3773}; 3774 3775static const unsigned int vin5_clk_a_mux[] = { 3776 VI5_CLK_A_MARK, 3777}; 3778 3779static const unsigned int vin5_clk_b_pins[] = { 3780 RCAR_GP_PIN(2, 22), 3781}; 3782 3783static const unsigned int vin5_clk_b_mux[] = { 3784 VI5_CLK_B_MARK, 3785}; 3786 3787static const struct { 3788 struct sh_pfc_pin_group common[261]; 3789#ifdef CONFIG_PINCTRL_PFC_R8A77990 3790 struct sh_pfc_pin_group automotive[22]; 3791#endif 3792} pinmux_groups = { 3793 .common = { 3794 SH_PFC_PIN_GROUP(audio_clk_a), 3795 SH_PFC_PIN_GROUP(audio_clk_b_a), 3796 SH_PFC_PIN_GROUP(audio_clk_b_b), 3797 SH_PFC_PIN_GROUP(audio_clk_b_c), 3798 SH_PFC_PIN_GROUP(audio_clk_c_a), 3799 SH_PFC_PIN_GROUP(audio_clk_c_b), 3800 SH_PFC_PIN_GROUP(audio_clk_c_c), 3801 SH_PFC_PIN_GROUP(audio_clkout_a), 3802 SH_PFC_PIN_GROUP(audio_clkout_b), 3803 SH_PFC_PIN_GROUP(audio_clkout1_a), 3804 SH_PFC_PIN_GROUP(audio_clkout1_b), 3805 SH_PFC_PIN_GROUP(audio_clkout1_c), 3806 SH_PFC_PIN_GROUP(audio_clkout2_a), 3807 SH_PFC_PIN_GROUP(audio_clkout2_b), 3808 SH_PFC_PIN_GROUP(audio_clkout2_c), 3809 SH_PFC_PIN_GROUP(audio_clkout3_a), 3810 SH_PFC_PIN_GROUP(audio_clkout3_b), 3811 SH_PFC_PIN_GROUP(audio_clkout3_c), 3812 SH_PFC_PIN_GROUP(avb_link), 3813 SH_PFC_PIN_GROUP(avb_magic), 3814 SH_PFC_PIN_GROUP(avb_phy_int), 3815 SH_PFC_PIN_GROUP(avb_mii), 3816 SH_PFC_PIN_GROUP(avb_avtp_pps), 3817 SH_PFC_PIN_GROUP(avb_avtp_match), 3818 SH_PFC_PIN_GROUP(avb_avtp_capture), 3819 SH_PFC_PIN_GROUP(can0_data), 3820 SH_PFC_PIN_GROUP(can1_data), 3821 SH_PFC_PIN_GROUP(can_clk), 3822 SH_PFC_PIN_GROUP(canfd0_data), 3823 SH_PFC_PIN_GROUP(canfd1_data), 3824 SH_PFC_PIN_GROUP(du_rgb666), 3825 SH_PFC_PIN_GROUP(du_rgb888), 3826 SH_PFC_PIN_GROUP(du_clk_in_0), 3827 SH_PFC_PIN_GROUP(du_clk_in_1), 3828 SH_PFC_PIN_GROUP(du_clk_out_0), 3829 SH_PFC_PIN_GROUP(du_sync), 3830 SH_PFC_PIN_GROUP(du_disp_cde), 3831 SH_PFC_PIN_GROUP(du_cde), 3832 SH_PFC_PIN_GROUP(du_disp), 3833 SH_PFC_PIN_GROUP(hscif0_data_a), 3834 SH_PFC_PIN_GROUP(hscif0_clk_a), 3835 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 3836 SH_PFC_PIN_GROUP(hscif0_data_b), 3837 SH_PFC_PIN_GROUP(hscif0_clk_b), 3838 SH_PFC_PIN_GROUP(hscif1_data_a), 3839 SH_PFC_PIN_GROUP(hscif1_clk_a), 3840 SH_PFC_PIN_GROUP(hscif1_data_b), 3841 SH_PFC_PIN_GROUP(hscif1_clk_b), 3842 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3843 SH_PFC_PIN_GROUP(hscif2_data_a), 3844 SH_PFC_PIN_GROUP(hscif2_clk_a), 3845 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 3846 SH_PFC_PIN_GROUP(hscif2_data_b), 3847 SH_PFC_PIN_GROUP(hscif3_data_a), 3848 SH_PFC_PIN_GROUP(hscif3_data_b), 3849 SH_PFC_PIN_GROUP(hscif3_clk_b), 3850 SH_PFC_PIN_GROUP(hscif3_data_c), 3851 SH_PFC_PIN_GROUP(hscif3_clk_c), 3852 SH_PFC_PIN_GROUP(hscif3_ctrl_c), 3853 SH_PFC_PIN_GROUP(hscif3_data_d), 3854 SH_PFC_PIN_GROUP(hscif3_data_e), 3855 SH_PFC_PIN_GROUP(hscif3_ctrl_e), 3856 SH_PFC_PIN_GROUP(hscif4_data_a), 3857 SH_PFC_PIN_GROUP(hscif4_clk_a), 3858 SH_PFC_PIN_GROUP(hscif4_ctrl_a), 3859 SH_PFC_PIN_GROUP(hscif4_data_b), 3860 SH_PFC_PIN_GROUP(hscif4_clk_b), 3861 SH_PFC_PIN_GROUP(hscif4_data_c), 3862 SH_PFC_PIN_GROUP(hscif4_data_d), 3863 SH_PFC_PIN_GROUP(hscif4_data_e), 3864 SH_PFC_PIN_GROUP(i2c1_a), 3865 SH_PFC_PIN_GROUP(i2c1_b), 3866 SH_PFC_PIN_GROUP(i2c1_c), 3867 SH_PFC_PIN_GROUP(i2c1_d), 3868 SH_PFC_PIN_GROUP(i2c2_a), 3869 SH_PFC_PIN_GROUP(i2c2_b), 3870 SH_PFC_PIN_GROUP(i2c2_c), 3871 SH_PFC_PIN_GROUP(i2c2_d), 3872 SH_PFC_PIN_GROUP(i2c2_e), 3873 SH_PFC_PIN_GROUP(i2c4), 3874 SH_PFC_PIN_GROUP(i2c5), 3875 SH_PFC_PIN_GROUP(i2c6_a), 3876 SH_PFC_PIN_GROUP(i2c6_b), 3877 SH_PFC_PIN_GROUP(i2c7_a), 3878 SH_PFC_PIN_GROUP(i2c7_b), 3879 SH_PFC_PIN_GROUP(intc_ex_irq0), 3880 SH_PFC_PIN_GROUP(intc_ex_irq1), 3881 SH_PFC_PIN_GROUP(intc_ex_irq2), 3882 SH_PFC_PIN_GROUP(intc_ex_irq3), 3883 SH_PFC_PIN_GROUP(intc_ex_irq4), 3884 SH_PFC_PIN_GROUP(intc_ex_irq5), 3885 SH_PFC_PIN_GROUP(msiof0_clk), 3886 SH_PFC_PIN_GROUP(msiof0_sync), 3887 SH_PFC_PIN_GROUP(msiof0_ss1), 3888 SH_PFC_PIN_GROUP(msiof0_ss2), 3889 SH_PFC_PIN_GROUP(msiof0_txd), 3890 SH_PFC_PIN_GROUP(msiof0_rxd), 3891 SH_PFC_PIN_GROUP(msiof1_clk), 3892 SH_PFC_PIN_GROUP(msiof1_sync), 3893 SH_PFC_PIN_GROUP(msiof1_ss1), 3894 SH_PFC_PIN_GROUP(msiof1_ss2), 3895 SH_PFC_PIN_GROUP(msiof1_txd), 3896 SH_PFC_PIN_GROUP(msiof1_rxd), 3897 SH_PFC_PIN_GROUP(msiof2_clk_a), 3898 SH_PFC_PIN_GROUP(msiof2_sync_a), 3899 SH_PFC_PIN_GROUP(msiof2_ss1_a), 3900 SH_PFC_PIN_GROUP(msiof2_ss2_a), 3901 SH_PFC_PIN_GROUP(msiof2_txd_a), 3902 SH_PFC_PIN_GROUP(msiof2_rxd_a), 3903 SH_PFC_PIN_GROUP(msiof2_clk_b), 3904 SH_PFC_PIN_GROUP(msiof2_sync_b), 3905 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3906 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3907 SH_PFC_PIN_GROUP(msiof2_txd_b), 3908 SH_PFC_PIN_GROUP(msiof2_rxd_b), 3909 SH_PFC_PIN_GROUP(msiof3_clk_a), 3910 SH_PFC_PIN_GROUP(msiof3_sync_a), 3911 SH_PFC_PIN_GROUP(msiof3_ss1_a), 3912 SH_PFC_PIN_GROUP(msiof3_ss2_a), 3913 SH_PFC_PIN_GROUP(msiof3_txd_a), 3914 SH_PFC_PIN_GROUP(msiof3_rxd_a), 3915 SH_PFC_PIN_GROUP(msiof3_clk_b), 3916 SH_PFC_PIN_GROUP(msiof3_sync_b), 3917 SH_PFC_PIN_GROUP(msiof3_ss1_b), 3918 SH_PFC_PIN_GROUP(msiof3_txd_b), 3919 SH_PFC_PIN_GROUP(msiof3_rxd_b), 3920 SH_PFC_PIN_GROUP(pwm0_a), 3921 SH_PFC_PIN_GROUP(pwm0_b), 3922 SH_PFC_PIN_GROUP(pwm1_a), 3923 SH_PFC_PIN_GROUP(pwm1_b), 3924 SH_PFC_PIN_GROUP(pwm2_a), 3925 SH_PFC_PIN_GROUP(pwm2_b), 3926 SH_PFC_PIN_GROUP(pwm2_c), 3927 SH_PFC_PIN_GROUP(pwm3_a), 3928 SH_PFC_PIN_GROUP(pwm3_b), 3929 SH_PFC_PIN_GROUP(pwm3_c), 3930 SH_PFC_PIN_GROUP(pwm4_a), 3931 SH_PFC_PIN_GROUP(pwm4_b), 3932 SH_PFC_PIN_GROUP(pwm5_a), 3933 SH_PFC_PIN_GROUP(pwm5_b), 3934 SH_PFC_PIN_GROUP(pwm6_a), 3935 SH_PFC_PIN_GROUP(pwm6_b), 3936 SH_PFC_PIN_GROUP(qspi0_ctrl), 3937 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), 3938 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), 3939 SH_PFC_PIN_GROUP(qspi1_ctrl), 3940 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), 3941 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), 3942 BUS_DATA_PIN_GROUP(rpc_clk, 1), 3943 BUS_DATA_PIN_GROUP(rpc_clk, 2), 3944 SH_PFC_PIN_GROUP(rpc_ctrl), 3945 SH_PFC_PIN_GROUP(rpc_data), 3946 SH_PFC_PIN_GROUP(rpc_reset), 3947 SH_PFC_PIN_GROUP(rpc_int), 3948 SH_PFC_PIN_GROUP(scif0_data_a), 3949 SH_PFC_PIN_GROUP(scif0_clk_a), 3950 SH_PFC_PIN_GROUP(scif0_ctrl_a), 3951 SH_PFC_PIN_GROUP(scif0_data_b), 3952 SH_PFC_PIN_GROUP(scif0_clk_b), 3953 SH_PFC_PIN_GROUP(scif1_data), 3954 SH_PFC_PIN_GROUP(scif1_clk), 3955 SH_PFC_PIN_GROUP(scif1_ctrl), 3956 SH_PFC_PIN_GROUP(scif2_data_a), 3957 SH_PFC_PIN_GROUP(scif2_clk_a), 3958 SH_PFC_PIN_GROUP(scif2_data_b), 3959 SH_PFC_PIN_GROUP(scif3_data_a), 3960 SH_PFC_PIN_GROUP(scif3_clk_a), 3961 SH_PFC_PIN_GROUP(scif3_ctrl_a), 3962 SH_PFC_PIN_GROUP(scif3_data_b), 3963 SH_PFC_PIN_GROUP(scif3_data_c), 3964 SH_PFC_PIN_GROUP(scif3_clk_c), 3965 SH_PFC_PIN_GROUP(scif4_data_a), 3966 SH_PFC_PIN_GROUP(scif4_clk_a), 3967 SH_PFC_PIN_GROUP(scif4_ctrl_a), 3968 SH_PFC_PIN_GROUP(scif4_data_b), 3969 SH_PFC_PIN_GROUP(scif4_clk_b), 3970 SH_PFC_PIN_GROUP(scif4_data_c), 3971 SH_PFC_PIN_GROUP(scif4_ctrl_c), 3972 SH_PFC_PIN_GROUP(scif5_data_a), 3973 SH_PFC_PIN_GROUP(scif5_clk_a), 3974 SH_PFC_PIN_GROUP(scif5_data_b), 3975 SH_PFC_PIN_GROUP(scif5_data_c), 3976 SH_PFC_PIN_GROUP(scif_clk_a), 3977 SH_PFC_PIN_GROUP(scif_clk_b), 3978 BUS_DATA_PIN_GROUP(sdhi0_data, 1), 3979 BUS_DATA_PIN_GROUP(sdhi0_data, 4), 3980 SH_PFC_PIN_GROUP(sdhi0_ctrl), 3981 SH_PFC_PIN_GROUP(sdhi0_cd), 3982 SH_PFC_PIN_GROUP(sdhi0_wp), 3983 BUS_DATA_PIN_GROUP(sdhi1_data, 1), 3984 BUS_DATA_PIN_GROUP(sdhi1_data, 4), 3985 SH_PFC_PIN_GROUP(sdhi1_ctrl), 3986 SH_PFC_PIN_GROUP(sdhi1_cd), 3987 SH_PFC_PIN_GROUP(sdhi1_wp), 3988 BUS_DATA_PIN_GROUP(sdhi3_data, 1), 3989 BUS_DATA_PIN_GROUP(sdhi3_data, 4), 3990 BUS_DATA_PIN_GROUP(sdhi3_data, 8), 3991 SH_PFC_PIN_GROUP(sdhi3_ctrl), 3992 SH_PFC_PIN_GROUP(sdhi3_cd), 3993 SH_PFC_PIN_GROUP(sdhi3_wp), 3994 SH_PFC_PIN_GROUP(sdhi3_ds), 3995 SH_PFC_PIN_GROUP(ssi0_data), 3996 SH_PFC_PIN_GROUP(ssi01239_ctrl), 3997 SH_PFC_PIN_GROUP(ssi1_data), 3998 SH_PFC_PIN_GROUP(ssi1_ctrl), 3999 SH_PFC_PIN_GROUP(ssi2_data), 4000 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4001 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4002 SH_PFC_PIN_GROUP(ssi3_data), 4003 SH_PFC_PIN_GROUP(ssi349_ctrl), 4004 SH_PFC_PIN_GROUP(ssi4_data), 4005 SH_PFC_PIN_GROUP(ssi4_ctrl), 4006 SH_PFC_PIN_GROUP(ssi5_data), 4007 SH_PFC_PIN_GROUP(ssi5_ctrl), 4008 SH_PFC_PIN_GROUP(ssi6_data), 4009 SH_PFC_PIN_GROUP(ssi6_ctrl), 4010 SH_PFC_PIN_GROUP(ssi7_data), 4011 SH_PFC_PIN_GROUP(ssi78_ctrl), 4012 SH_PFC_PIN_GROUP(ssi8_data), 4013 SH_PFC_PIN_GROUP(ssi9_data), 4014 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4015 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4016 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4017 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4018 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4019 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4020 SH_PFC_PIN_GROUP(usb0_a), 4021 SH_PFC_PIN_GROUP(usb0_b), 4022 SH_PFC_PIN_GROUP(usb0_id), 4023 SH_PFC_PIN_GROUP(usb30), 4024 SH_PFC_PIN_GROUP(usb30_id), 4025 BUS_DATA_PIN_GROUP(vin4_data, 8, _a), 4026 BUS_DATA_PIN_GROUP(vin4_data, 10, _a), 4027 BUS_DATA_PIN_GROUP(vin4_data, 12, _a), 4028 BUS_DATA_PIN_GROUP(vin4_data, 16, _a), 4029 SH_PFC_PIN_GROUP(vin4_data18_a), 4030 BUS_DATA_PIN_GROUP(vin4_data, 20, _a), 4031 BUS_DATA_PIN_GROUP(vin4_data, 24, _a), 4032 BUS_DATA_PIN_GROUP(vin4_data, 8, _b), 4033 BUS_DATA_PIN_GROUP(vin4_data, 10, _b), 4034 BUS_DATA_PIN_GROUP(vin4_data, 12, _b), 4035 BUS_DATA_PIN_GROUP(vin4_data, 16, _b), 4036 SH_PFC_PIN_GROUP(vin4_data18_b), 4037 BUS_DATA_PIN_GROUP(vin4_data, 20, _b), 4038 BUS_DATA_PIN_GROUP(vin4_data, 24, _b), 4039 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), 4040 SH_PFC_PIN_GROUP(vin4_sync), 4041 SH_PFC_PIN_GROUP(vin4_field), 4042 SH_PFC_PIN_GROUP(vin4_clkenb), 4043 SH_PFC_PIN_GROUP(vin4_clk), 4044 BUS_DATA_PIN_GROUP(vin5_data, 8, _a), 4045 BUS_DATA_PIN_GROUP(vin5_data, 10, _a), 4046 BUS_DATA_PIN_GROUP(vin5_data, 12, _a), 4047 BUS_DATA_PIN_GROUP(vin5_data, 16, _a), 4048 SH_PFC_PIN_GROUP(vin5_data8_b), 4049 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8), 4050 SH_PFC_PIN_GROUP(vin5_sync_a), 4051 SH_PFC_PIN_GROUP(vin5_field_a), 4052 SH_PFC_PIN_GROUP(vin5_clkenb_a), 4053 SH_PFC_PIN_GROUP(vin5_clk_a), 4054 SH_PFC_PIN_GROUP(vin5_clk_b), 4055 }, 4056#ifdef CONFIG_PINCTRL_PFC_R8A77990 4057 .automotive = { 4058 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4059 SH_PFC_PIN_GROUP(drif0_data0_a), 4060 SH_PFC_PIN_GROUP(drif0_data1_a), 4061 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4062 SH_PFC_PIN_GROUP(drif0_data0_b), 4063 SH_PFC_PIN_GROUP(drif0_data1_b), 4064 SH_PFC_PIN_GROUP(drif1_ctrl), 4065 SH_PFC_PIN_GROUP(drif1_data0), 4066 SH_PFC_PIN_GROUP(drif1_data1), 4067 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4068 SH_PFC_PIN_GROUP(drif2_data0_a), 4069 SH_PFC_PIN_GROUP(drif2_data1_a), 4070 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4071 SH_PFC_PIN_GROUP(drif2_data0_b), 4072 SH_PFC_PIN_GROUP(drif2_data1_b), 4073 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4074 SH_PFC_PIN_GROUP(drif3_data0_a), 4075 SH_PFC_PIN_GROUP(drif3_data1_a), 4076 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4077 SH_PFC_PIN_GROUP(drif3_data0_b), 4078 SH_PFC_PIN_GROUP(drif3_data1_b), 4079 SH_PFC_PIN_GROUP(mlb_3pin), 4080 } 4081#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4082}; 4083 4084static const char * const audio_clk_groups[] = { 4085 "audio_clk_a", 4086 "audio_clk_b_a", 4087 "audio_clk_b_b", 4088 "audio_clk_b_c", 4089 "audio_clk_c_a", 4090 "audio_clk_c_b", 4091 "audio_clk_c_c", 4092 "audio_clkout_a", 4093 "audio_clkout_b", 4094 "audio_clkout1_a", 4095 "audio_clkout1_b", 4096 "audio_clkout1_c", 4097 "audio_clkout2_a", 4098 "audio_clkout2_b", 4099 "audio_clkout2_c", 4100 "audio_clkout3_a", 4101 "audio_clkout3_b", 4102 "audio_clkout3_c", 4103}; 4104 4105static const char * const avb_groups[] = { 4106 "avb_link", 4107 "avb_magic", 4108 "avb_phy_int", 4109 "avb_mii", 4110 "avb_avtp_pps", 4111 "avb_avtp_match", 4112 "avb_avtp_capture", 4113}; 4114 4115static const char * const can0_groups[] = { 4116 "can0_data", 4117}; 4118 4119static const char * const can1_groups[] = { 4120 "can1_data", 4121}; 4122 4123static const char * const can_clk_groups[] = { 4124 "can_clk", 4125}; 4126 4127static const char * const canfd0_groups[] = { 4128 "canfd0_data", 4129}; 4130 4131static const char * const canfd1_groups[] = { 4132 "canfd1_data", 4133}; 4134 4135#ifdef CONFIG_PINCTRL_PFC_R8A77990 4136static const char * const drif0_groups[] = { 4137 "drif0_ctrl_a", 4138 "drif0_data0_a", 4139 "drif0_data1_a", 4140 "drif0_ctrl_b", 4141 "drif0_data0_b", 4142 "drif0_data1_b", 4143}; 4144 4145static const char * const drif1_groups[] = { 4146 "drif1_ctrl", 4147 "drif1_data0", 4148 "drif1_data1", 4149}; 4150 4151static const char * const drif2_groups[] = { 4152 "drif2_ctrl_a", 4153 "drif2_data0_a", 4154 "drif2_data1_a", 4155 "drif2_ctrl_b", 4156 "drif2_data0_b", 4157 "drif2_data1_b", 4158}; 4159 4160static const char * const drif3_groups[] = { 4161 "drif3_ctrl_a", 4162 "drif3_data0_a", 4163 "drif3_data1_a", 4164 "drif3_ctrl_b", 4165 "drif3_data0_b", 4166 "drif3_data1_b", 4167}; 4168#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4169 4170static const char * const du_groups[] = { 4171 "du_rgb666", 4172 "du_rgb888", 4173 "du_clk_in_0", 4174 "du_clk_in_1", 4175 "du_clk_out_0", 4176 "du_sync", 4177 "du_disp_cde", 4178 "du_cde", 4179 "du_disp", 4180}; 4181 4182static const char * const hscif0_groups[] = { 4183 "hscif0_data_a", 4184 "hscif0_clk_a", 4185 "hscif0_ctrl_a", 4186 "hscif0_data_b", 4187 "hscif0_clk_b", 4188}; 4189 4190static const char * const hscif1_groups[] = { 4191 "hscif1_data_a", 4192 "hscif1_clk_a", 4193 "hscif1_data_b", 4194 "hscif1_clk_b", 4195 "hscif1_ctrl_b", 4196}; 4197 4198static const char * const hscif2_groups[] = { 4199 "hscif2_data_a", 4200 "hscif2_clk_a", 4201 "hscif2_ctrl_a", 4202 "hscif2_data_b", 4203}; 4204 4205static const char * const hscif3_groups[] = { 4206 "hscif3_data_a", 4207 "hscif3_data_b", 4208 "hscif3_clk_b", 4209 "hscif3_data_c", 4210 "hscif3_clk_c", 4211 "hscif3_ctrl_c", 4212 "hscif3_data_d", 4213 "hscif3_data_e", 4214 "hscif3_ctrl_e", 4215}; 4216 4217static const char * const hscif4_groups[] = { 4218 "hscif4_data_a", 4219 "hscif4_clk_a", 4220 "hscif4_ctrl_a", 4221 "hscif4_data_b", 4222 "hscif4_clk_b", 4223 "hscif4_data_c", 4224 "hscif4_data_d", 4225 "hscif4_data_e", 4226}; 4227 4228static const char * const i2c1_groups[] = { 4229 "i2c1_a", 4230 "i2c1_b", 4231 "i2c1_c", 4232 "i2c1_d", 4233}; 4234 4235static const char * const i2c2_groups[] = { 4236 "i2c2_a", 4237 "i2c2_b", 4238 "i2c2_c", 4239 "i2c2_d", 4240 "i2c2_e", 4241}; 4242 4243static const char * const i2c4_groups[] = { 4244 "i2c4", 4245}; 4246 4247static const char * const i2c5_groups[] = { 4248 "i2c5", 4249}; 4250 4251static const char * const i2c6_groups[] = { 4252 "i2c6_a", 4253 "i2c6_b", 4254}; 4255 4256static const char * const i2c7_groups[] = { 4257 "i2c7_a", 4258 "i2c7_b", 4259}; 4260 4261static const char * const intc_ex_groups[] = { 4262 "intc_ex_irq0", 4263 "intc_ex_irq1", 4264 "intc_ex_irq2", 4265 "intc_ex_irq3", 4266 "intc_ex_irq4", 4267 "intc_ex_irq5", 4268}; 4269 4270#ifdef CONFIG_PINCTRL_PFC_R8A77990 4271static const char * const mlb_3pin_groups[] = { 4272 "mlb_3pin", 4273}; 4274#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4275 4276static const char * const msiof0_groups[] = { 4277 "msiof0_clk", 4278 "msiof0_sync", 4279 "msiof0_ss1", 4280 "msiof0_ss2", 4281 "msiof0_txd", 4282 "msiof0_rxd", 4283}; 4284 4285static const char * const msiof1_groups[] = { 4286 "msiof1_clk", 4287 "msiof1_sync", 4288 "msiof1_ss1", 4289 "msiof1_ss2", 4290 "msiof1_txd", 4291 "msiof1_rxd", 4292}; 4293 4294static const char * const msiof2_groups[] = { 4295 "msiof2_clk_a", 4296 "msiof2_sync_a", 4297 "msiof2_ss1_a", 4298 "msiof2_ss2_a", 4299 "msiof2_txd_a", 4300 "msiof2_rxd_a", 4301 "msiof2_clk_b", 4302 "msiof2_sync_b", 4303 "msiof2_ss1_b", 4304 "msiof2_ss2_b", 4305 "msiof2_txd_b", 4306 "msiof2_rxd_b", 4307}; 4308 4309static const char * const msiof3_groups[] = { 4310 "msiof3_clk_a", 4311 "msiof3_sync_a", 4312 "msiof3_ss1_a", 4313 "msiof3_ss2_a", 4314 "msiof3_txd_a", 4315 "msiof3_rxd_a", 4316 "msiof3_clk_b", 4317 "msiof3_sync_b", 4318 "msiof3_ss1_b", 4319 "msiof3_txd_b", 4320 "msiof3_rxd_b", 4321}; 4322 4323static const char * const pwm0_groups[] = { 4324 "pwm0_a", 4325 "pwm0_b", 4326}; 4327 4328static const char * const pwm1_groups[] = { 4329 "pwm1_a", 4330 "pwm1_b", 4331}; 4332 4333static const char * const pwm2_groups[] = { 4334 "pwm2_a", 4335 "pwm2_b", 4336 "pwm2_c", 4337}; 4338 4339static const char * const pwm3_groups[] = { 4340 "pwm3_a", 4341 "pwm3_b", 4342 "pwm3_c", 4343}; 4344 4345static const char * const pwm4_groups[] = { 4346 "pwm4_a", 4347 "pwm4_b", 4348}; 4349 4350static const char * const pwm5_groups[] = { 4351 "pwm5_a", 4352 "pwm5_b", 4353}; 4354 4355static const char * const pwm6_groups[] = { 4356 "pwm6_a", 4357 "pwm6_b", 4358}; 4359 4360static const char * const qspi0_groups[] = { 4361 "qspi0_ctrl", 4362 "qspi0_data2", 4363 "qspi0_data4", 4364}; 4365 4366static const char * const qspi1_groups[] = { 4367 "qspi1_ctrl", 4368 "qspi1_data2", 4369 "qspi1_data4", 4370}; 4371 4372static const char * const rpc_groups[] = { 4373 "rpc_clk1", 4374 "rpc_clk2", 4375 "rpc_ctrl", 4376 "rpc_data", 4377 "rpc_reset", 4378 "rpc_int", 4379}; 4380 4381static const char * const scif0_groups[] = { 4382 "scif0_data_a", 4383 "scif0_clk_a", 4384 "scif0_ctrl_a", 4385 "scif0_data_b", 4386 "scif0_clk_b", 4387}; 4388 4389static const char * const scif1_groups[] = { 4390 "scif1_data", 4391 "scif1_clk", 4392 "scif1_ctrl", 4393}; 4394 4395static const char * const scif2_groups[] = { 4396 "scif2_data_a", 4397 "scif2_clk_a", 4398 "scif2_data_b", 4399}; 4400 4401static const char * const scif3_groups[] = { 4402 "scif3_data_a", 4403 "scif3_clk_a", 4404 "scif3_ctrl_a", 4405 "scif3_data_b", 4406 "scif3_data_c", 4407 "scif3_clk_c", 4408}; 4409 4410static const char * const scif4_groups[] = { 4411 "scif4_data_a", 4412 "scif4_clk_a", 4413 "scif4_ctrl_a", 4414 "scif4_data_b", 4415 "scif4_clk_b", 4416 "scif4_data_c", 4417 "scif4_ctrl_c", 4418}; 4419 4420static const char * const scif5_groups[] = { 4421 "scif5_data_a", 4422 "scif5_clk_a", 4423 "scif5_data_b", 4424 "scif5_data_c", 4425}; 4426 4427static const char * const scif_clk_groups[] = { 4428 "scif_clk_a", 4429 "scif_clk_b", 4430}; 4431 4432static const char * const sdhi0_groups[] = { 4433 "sdhi0_data1", 4434 "sdhi0_data4", 4435 "sdhi0_ctrl", 4436 "sdhi0_cd", 4437 "sdhi0_wp", 4438}; 4439 4440static const char * const sdhi1_groups[] = { 4441 "sdhi1_data1", 4442 "sdhi1_data4", 4443 "sdhi1_ctrl", 4444 "sdhi1_cd", 4445 "sdhi1_wp", 4446}; 4447 4448static const char * const sdhi3_groups[] = { 4449 "sdhi3_data1", 4450 "sdhi3_data4", 4451 "sdhi3_data8", 4452 "sdhi3_ctrl", 4453 "sdhi3_cd", 4454 "sdhi3_wp", 4455 "sdhi3_ds", 4456}; 4457 4458static const char * const ssi_groups[] = { 4459 "ssi0_data", 4460 "ssi01239_ctrl", 4461 "ssi1_data", 4462 "ssi1_ctrl", 4463 "ssi2_data", 4464 "ssi2_ctrl_a", 4465 "ssi2_ctrl_b", 4466 "ssi3_data", 4467 "ssi349_ctrl", 4468 "ssi4_data", 4469 "ssi4_ctrl", 4470 "ssi5_data", 4471 "ssi5_ctrl", 4472 "ssi6_data", 4473 "ssi6_ctrl", 4474 "ssi7_data", 4475 "ssi78_ctrl", 4476 "ssi8_data", 4477 "ssi9_data", 4478 "ssi9_ctrl_a", 4479 "ssi9_ctrl_b", 4480}; 4481 4482static const char * const tmu_groups[] = { 4483 "tmu_tclk1_a", 4484 "tmu_tclk1_b", 4485 "tmu_tclk2_a", 4486 "tmu_tclk2_b", 4487}; 4488 4489static const char * const usb0_groups[] = { 4490 "usb0_a", 4491 "usb0_b", 4492 "usb0_id", 4493}; 4494 4495static const char * const usb30_groups[] = { 4496 "usb30", 4497 "usb30_id", 4498}; 4499 4500static const char * const vin4_groups[] = { 4501 "vin4_data8_a", 4502 "vin4_data10_a", 4503 "vin4_data12_a", 4504 "vin4_data16_a", 4505 "vin4_data18_a", 4506 "vin4_data20_a", 4507 "vin4_data24_a", 4508 "vin4_data8_b", 4509 "vin4_data10_b", 4510 "vin4_data12_b", 4511 "vin4_data16_b", 4512 "vin4_data18_b", 4513 "vin4_data20_b", 4514 "vin4_data24_b", 4515 "vin4_g8", 4516 "vin4_sync", 4517 "vin4_field", 4518 "vin4_clkenb", 4519 "vin4_clk", 4520}; 4521 4522static const char * const vin5_groups[] = { 4523 "vin5_data8_a", 4524 "vin5_data10_a", 4525 "vin5_data12_a", 4526 "vin5_data16_a", 4527 "vin5_data8_b", 4528 "vin5_high8", 4529 "vin5_sync_a", 4530 "vin5_field_a", 4531 "vin5_clkenb_a", 4532 "vin5_clk_a", 4533 "vin5_clk_b", 4534}; 4535 4536static const struct { 4537 struct sh_pfc_function common[50]; 4538#ifdef CONFIG_PINCTRL_PFC_R8A77990 4539 struct sh_pfc_function automotive[5]; 4540#endif 4541} pinmux_functions = { 4542 .common = { 4543 SH_PFC_FUNCTION(audio_clk), 4544 SH_PFC_FUNCTION(avb), 4545 SH_PFC_FUNCTION(can0), 4546 SH_PFC_FUNCTION(can1), 4547 SH_PFC_FUNCTION(can_clk), 4548 SH_PFC_FUNCTION(canfd0), 4549 SH_PFC_FUNCTION(canfd1), 4550 SH_PFC_FUNCTION(du), 4551 SH_PFC_FUNCTION(hscif0), 4552 SH_PFC_FUNCTION(hscif1), 4553 SH_PFC_FUNCTION(hscif2), 4554 SH_PFC_FUNCTION(hscif3), 4555 SH_PFC_FUNCTION(hscif4), 4556 SH_PFC_FUNCTION(i2c1), 4557 SH_PFC_FUNCTION(i2c2), 4558 SH_PFC_FUNCTION(i2c4), 4559 SH_PFC_FUNCTION(i2c5), 4560 SH_PFC_FUNCTION(i2c6), 4561 SH_PFC_FUNCTION(i2c7), 4562 SH_PFC_FUNCTION(intc_ex), 4563 SH_PFC_FUNCTION(msiof0), 4564 SH_PFC_FUNCTION(msiof1), 4565 SH_PFC_FUNCTION(msiof2), 4566 SH_PFC_FUNCTION(msiof3), 4567 SH_PFC_FUNCTION(pwm0), 4568 SH_PFC_FUNCTION(pwm1), 4569 SH_PFC_FUNCTION(pwm2), 4570 SH_PFC_FUNCTION(pwm3), 4571 SH_PFC_FUNCTION(pwm4), 4572 SH_PFC_FUNCTION(pwm5), 4573 SH_PFC_FUNCTION(pwm6), 4574 SH_PFC_FUNCTION(qspi0), 4575 SH_PFC_FUNCTION(qspi1), 4576 SH_PFC_FUNCTION(rpc), 4577 SH_PFC_FUNCTION(scif0), 4578 SH_PFC_FUNCTION(scif1), 4579 SH_PFC_FUNCTION(scif2), 4580 SH_PFC_FUNCTION(scif3), 4581 SH_PFC_FUNCTION(scif4), 4582 SH_PFC_FUNCTION(scif5), 4583 SH_PFC_FUNCTION(scif_clk), 4584 SH_PFC_FUNCTION(sdhi0), 4585 SH_PFC_FUNCTION(sdhi1), 4586 SH_PFC_FUNCTION(sdhi3), 4587 SH_PFC_FUNCTION(ssi), 4588 SH_PFC_FUNCTION(tmu), 4589 SH_PFC_FUNCTION(usb0), 4590 SH_PFC_FUNCTION(usb30), 4591 SH_PFC_FUNCTION(vin4), 4592 SH_PFC_FUNCTION(vin5), 4593 }, 4594#ifdef CONFIG_PINCTRL_PFC_R8A77990 4595 .automotive = { 4596 SH_PFC_FUNCTION(drif0), 4597 SH_PFC_FUNCTION(drif1), 4598 SH_PFC_FUNCTION(drif2), 4599 SH_PFC_FUNCTION(drif3), 4600 SH_PFC_FUNCTION(mlb_3pin), 4601 } 4602#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4603}; 4604 4605static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4606#define F_(x, y) FN_##y 4607#define FM(x) FN_##x 4608 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, 4609 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4610 1, 1, 1, 1, 1, 1, 1), 4611 GROUP( 4612 /* GP0_31_18 RESERVED */ 4613 GP_0_17_FN, GPSR0_17, 4614 GP_0_16_FN, GPSR0_16, 4615 GP_0_15_FN, GPSR0_15, 4616 GP_0_14_FN, GPSR0_14, 4617 GP_0_13_FN, GPSR0_13, 4618 GP_0_12_FN, GPSR0_12, 4619 GP_0_11_FN, GPSR0_11, 4620 GP_0_10_FN, GPSR0_10, 4621 GP_0_9_FN, GPSR0_9, 4622 GP_0_8_FN, GPSR0_8, 4623 GP_0_7_FN, GPSR0_7, 4624 GP_0_6_FN, GPSR0_6, 4625 GP_0_5_FN, GPSR0_5, 4626 GP_0_4_FN, GPSR0_4, 4627 GP_0_3_FN, GPSR0_3, 4628 GP_0_2_FN, GPSR0_2, 4629 GP_0_1_FN, GPSR0_1, 4630 GP_0_0_FN, GPSR0_0, )) 4631 }, 4632 { PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32, 4633 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 4635 GROUP( 4636 /* GP1_31_23 RESERVED */ 4637 GP_1_22_FN, GPSR1_22, 4638 GP_1_21_FN, GPSR1_21, 4639 GP_1_20_FN, GPSR1_20, 4640 GP_1_19_FN, GPSR1_19, 4641 GP_1_18_FN, GPSR1_18, 4642 GP_1_17_FN, GPSR1_17, 4643 GP_1_16_FN, GPSR1_16, 4644 GP_1_15_FN, GPSR1_15, 4645 GP_1_14_FN, GPSR1_14, 4646 GP_1_13_FN, GPSR1_13, 4647 GP_1_12_FN, GPSR1_12, 4648 GP_1_11_FN, GPSR1_11, 4649 GP_1_10_FN, GPSR1_10, 4650 GP_1_9_FN, GPSR1_9, 4651 GP_1_8_FN, GPSR1_8, 4652 GP_1_7_FN, GPSR1_7, 4653 GP_1_6_FN, GPSR1_6, 4654 GP_1_5_FN, GPSR1_5, 4655 GP_1_4_FN, GPSR1_4, 4656 GP_1_3_FN, GPSR1_3, 4657 GP_1_2_FN, GPSR1_2, 4658 GP_1_1_FN, GPSR1_1, 4659 GP_1_0_FN, GPSR1_0, )) 4660 }, 4661 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 4662 0, 0, 4663 0, 0, 4664 0, 0, 4665 0, 0, 4666 0, 0, 4667 0, 0, 4668 GP_2_25_FN, GPSR2_25, 4669 GP_2_24_FN, GPSR2_24, 4670 GP_2_23_FN, GPSR2_23, 4671 GP_2_22_FN, GPSR2_22, 4672 GP_2_21_FN, GPSR2_21, 4673 GP_2_20_FN, GPSR2_20, 4674 GP_2_19_FN, GPSR2_19, 4675 GP_2_18_FN, GPSR2_18, 4676 GP_2_17_FN, GPSR2_17, 4677 GP_2_16_FN, GPSR2_16, 4678 GP_2_15_FN, GPSR2_15, 4679 GP_2_14_FN, GPSR2_14, 4680 GP_2_13_FN, GPSR2_13, 4681 GP_2_12_FN, GPSR2_12, 4682 GP_2_11_FN, GPSR2_11, 4683 GP_2_10_FN, GPSR2_10, 4684 GP_2_9_FN, GPSR2_9, 4685 GP_2_8_FN, GPSR2_8, 4686 GP_2_7_FN, GPSR2_7, 4687 GP_2_6_FN, GPSR2_6, 4688 GP_2_5_FN, GPSR2_5, 4689 GP_2_4_FN, GPSR2_4, 4690 GP_2_3_FN, GPSR2_3, 4691 GP_2_2_FN, GPSR2_2, 4692 GP_2_1_FN, GPSR2_1, 4693 GP_2_0_FN, GPSR2_0, )) 4694 }, 4695 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, 4696 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4697 1, 1, 1, 1, 1), 4698 GROUP( 4699 /* GP3_31_16 RESERVED */ 4700 GP_3_15_FN, GPSR3_15, 4701 GP_3_14_FN, GPSR3_14, 4702 GP_3_13_FN, GPSR3_13, 4703 GP_3_12_FN, GPSR3_12, 4704 GP_3_11_FN, GPSR3_11, 4705 GP_3_10_FN, GPSR3_10, 4706 GP_3_9_FN, GPSR3_9, 4707 GP_3_8_FN, GPSR3_8, 4708 GP_3_7_FN, GPSR3_7, 4709 GP_3_6_FN, GPSR3_6, 4710 GP_3_5_FN, GPSR3_5, 4711 GP_3_4_FN, GPSR3_4, 4712 GP_3_3_FN, GPSR3_3, 4713 GP_3_2_FN, GPSR3_2, 4714 GP_3_1_FN, GPSR3_1, 4715 GP_3_0_FN, GPSR3_0, )) 4716 }, 4717 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, 4718 GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 4719 GROUP( 4720 /* GP4_31_11 RESERVED */ 4721 GP_4_10_FN, GPSR4_10, 4722 GP_4_9_FN, GPSR4_9, 4723 GP_4_8_FN, GPSR4_8, 4724 GP_4_7_FN, GPSR4_7, 4725 GP_4_6_FN, GPSR4_6, 4726 GP_4_5_FN, GPSR4_5, 4727 GP_4_4_FN, GPSR4_4, 4728 GP_4_3_FN, GPSR4_3, 4729 GP_4_2_FN, GPSR4_2, 4730 GP_4_1_FN, GPSR4_1, 4731 GP_4_0_FN, GPSR4_0, )) 4732 }, 4733 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, 4734 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4735 1, 1, 1, 1, 1, 1, 1, 1, 1), 4736 GROUP( 4737 /* GP5_31_20 RESERVED */ 4738 GP_5_19_FN, GPSR5_19, 4739 GP_5_18_FN, GPSR5_18, 4740 GP_5_17_FN, GPSR5_17, 4741 GP_5_16_FN, GPSR5_16, 4742 GP_5_15_FN, GPSR5_15, 4743 GP_5_14_FN, GPSR5_14, 4744 GP_5_13_FN, GPSR5_13, 4745 GP_5_12_FN, GPSR5_12, 4746 GP_5_11_FN, GPSR5_11, 4747 GP_5_10_FN, GPSR5_10, 4748 GP_5_9_FN, GPSR5_9, 4749 GP_5_8_FN, GPSR5_8, 4750 GP_5_7_FN, GPSR5_7, 4751 GP_5_6_FN, GPSR5_6, 4752 GP_5_5_FN, GPSR5_5, 4753 GP_5_4_FN, GPSR5_4, 4754 GP_5_3_FN, GPSR5_3, 4755 GP_5_2_FN, GPSR5_2, 4756 GP_5_1_FN, GPSR5_1, 4757 GP_5_0_FN, GPSR5_0, )) 4758 }, 4759 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32, 4760 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4761 1, 1, 1, 1, 1, 1, 1), 4762 GROUP( 4763 /* GP6_31_18 RESERVED */ 4764 GP_6_17_FN, GPSR6_17, 4765 GP_6_16_FN, GPSR6_16, 4766 GP_6_15_FN, GPSR6_15, 4767 GP_6_14_FN, GPSR6_14, 4768 GP_6_13_FN, GPSR6_13, 4769 GP_6_12_FN, GPSR6_12, 4770 GP_6_11_FN, GPSR6_11, 4771 GP_6_10_FN, GPSR6_10, 4772 GP_6_9_FN, GPSR6_9, 4773 GP_6_8_FN, GPSR6_8, 4774 GP_6_7_FN, GPSR6_7, 4775 GP_6_6_FN, GPSR6_6, 4776 GP_6_5_FN, GPSR6_5, 4777 GP_6_4_FN, GPSR6_4, 4778 GP_6_3_FN, GPSR6_3, 4779 GP_6_2_FN, GPSR6_2, 4780 GP_6_1_FN, GPSR6_1, 4781 GP_6_0_FN, GPSR6_0, )) 4782 }, 4783#undef F_ 4784#undef FM 4785 4786#define F_(x, y) x, 4787#define FM(x) FN_##x, 4788 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 4789 IP0_31_28 4790 IP0_27_24 4791 IP0_23_20 4792 IP0_19_16 4793 IP0_15_12 4794 IP0_11_8 4795 IP0_7_4 4796 IP0_3_0 )) 4797 }, 4798 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 4799 IP1_31_28 4800 IP1_27_24 4801 IP1_23_20 4802 IP1_19_16 4803 IP1_15_12 4804 IP1_11_8 4805 IP1_7_4 4806 IP1_3_0 )) 4807 }, 4808 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 4809 IP2_31_28 4810 IP2_27_24 4811 IP2_23_20 4812 IP2_19_16 4813 IP2_15_12 4814 IP2_11_8 4815 IP2_7_4 4816 IP2_3_0 )) 4817 }, 4818 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 4819 IP3_31_28 4820 IP3_27_24 4821 IP3_23_20 4822 IP3_19_16 4823 IP3_15_12 4824 IP3_11_8 4825 IP3_7_4 4826 IP3_3_0 )) 4827 }, 4828 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 4829 IP4_31_28 4830 IP4_27_24 4831 IP4_23_20 4832 IP4_19_16 4833 IP4_15_12 4834 IP4_11_8 4835 IP4_7_4 4836 IP4_3_0 )) 4837 }, 4838 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 4839 IP5_31_28 4840 IP5_27_24 4841 IP5_23_20 4842 IP5_19_16 4843 IP5_15_12 4844 IP5_11_8 4845 IP5_7_4 4846 IP5_3_0 )) 4847 }, 4848 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 4849 IP6_31_28 4850 IP6_27_24 4851 IP6_23_20 4852 IP6_19_16 4853 IP6_15_12 4854 IP6_11_8 4855 IP6_7_4 4856 IP6_3_0 )) 4857 }, 4858 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 4859 IP7_31_28 4860 IP7_27_24 4861 IP7_23_20 4862 IP7_19_16 4863 IP7_15_12 4864 IP7_11_8 4865 IP7_7_4 4866 IP7_3_0 )) 4867 }, 4868 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 4869 IP8_31_28 4870 IP8_27_24 4871 IP8_23_20 4872 IP8_19_16 4873 IP8_15_12 4874 IP8_11_8 4875 IP8_7_4 4876 IP8_3_0 )) 4877 }, 4878 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 4879 IP9_31_28 4880 IP9_27_24 4881 IP9_23_20 4882 IP9_19_16 4883 IP9_15_12 4884 IP9_11_8 4885 IP9_7_4 4886 IP9_3_0 )) 4887 }, 4888 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 4889 IP10_31_28 4890 IP10_27_24 4891 IP10_23_20 4892 IP10_19_16 4893 IP10_15_12 4894 IP10_11_8 4895 IP10_7_4 4896 IP10_3_0 )) 4897 }, 4898 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 4899 IP11_31_28 4900 IP11_27_24 4901 IP11_23_20 4902 IP11_19_16 4903 IP11_15_12 4904 IP11_11_8 4905 IP11_7_4 4906 IP11_3_0 )) 4907 }, 4908 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 4909 IP12_31_28 4910 IP12_27_24 4911 IP12_23_20 4912 IP12_19_16 4913 IP12_15_12 4914 IP12_11_8 4915 IP12_7_4 4916 IP12_3_0 )) 4917 }, 4918 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 4919 IP13_31_28 4920 IP13_27_24 4921 IP13_23_20 4922 IP13_19_16 4923 IP13_15_12 4924 IP13_11_8 4925 IP13_7_4 4926 IP13_3_0 )) 4927 }, 4928 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 4929 IP14_31_28 4930 IP14_27_24 4931 IP14_23_20 4932 IP14_19_16 4933 IP14_15_12 4934 IP14_11_8 4935 IP14_7_4 4936 IP14_3_0 )) 4937 }, 4938 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 4939 IP15_31_28 4940 IP15_27_24 4941 IP15_23_20 4942 IP15_19_16 4943 IP15_15_12 4944 IP15_11_8 4945 IP15_7_4 4946 IP15_3_0 )) 4947 }, 4948#undef F_ 4949#undef FM 4950 4951#define F_(x, y) x, 4952#define FM(x) FN_##x, 4953 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 4954 GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, 4955 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), 4956 GROUP( 4957 /* RESERVED 31 */ 4958 MOD_SEL0_30_29 4959 MOD_SEL0_28 4960 MOD_SEL0_27_26 4961 MOD_SEL0_25 4962 MOD_SEL0_24 4963 MOD_SEL0_23 4964 MOD_SEL0_22 4965 MOD_SEL0_21_20 4966 MOD_SEL0_19_18_17 4967 MOD_SEL0_16 4968 MOD_SEL0_15 4969 MOD_SEL0_14 4970 MOD_SEL0_13_12 4971 MOD_SEL0_11_10 4972 MOD_SEL0_9 4973 MOD_SEL0_8 4974 MOD_SEL0_7 4975 MOD_SEL0_6_5 4976 MOD_SEL0_4 4977 MOD_SEL0_3 4978 MOD_SEL0_2 4979 MOD_SEL0_1_0 )) 4980 }, 4981 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 4982 GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1, 4983 1, 2, 2, 2, 1, 1, 2, 1, -4), 4984 GROUP( 4985 MOD_SEL1_31 4986 MOD_SEL1_30 4987 MOD_SEL1_29 4988 MOD_SEL1_28 4989 /* RESERVED 27 */ 4990 MOD_SEL1_26 4991 MOD_SEL1_25 4992 MOD_SEL1_24_23_22 4993 MOD_SEL1_21_20_19 4994 MOD_SEL1_18 4995 MOD_SEL1_17 4996 MOD_SEL1_16 4997 MOD_SEL1_15 4998 MOD_SEL1_14_13 4999 MOD_SEL1_12_11 5000 MOD_SEL1_10_9 5001 MOD_SEL1_8 5002 MOD_SEL1_7 5003 MOD_SEL1_6_5 5004 MOD_SEL1_4 5005 /* RESERVED 3, 2, 1, 0 */ )) 5006 }, 5007 { /* sentinel */ } 5008}; 5009 5010static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5011 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5012 { RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */ 5013 { RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */ 5014 { RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */ 5015 { RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */ 5016 { RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */ 5017 { RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */ 5018 { RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */ 5019 } }, 5020 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5021 { RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */ 5022 { RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */ 5023 { RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */ 5024 { RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */ 5025 { RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */ 5026 { RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */ 5027 { RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */ 5028 { RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */ 5029 { RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */ 5030 { RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */ 5031 } }, 5032 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5033 { RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */ 5034 { RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */ 5035 { RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */ 5036 { RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */ 5037 { RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */ 5038 { RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */ 5039 } }, 5040 { /* sentinel */ } 5041}; 5042 5043enum ioctrl_regs { 5044 POCCTRL0, 5045 POCCTRL2, 5046 TDSELCTRL, 5047}; 5048 5049static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5050 [POCCTRL0] = { 0xe6060380, }, 5051 [POCCTRL2] = { 0xe6060388, }, 5052 [TDSELCTRL] = { 0xe60603c0, }, 5053 { /* sentinel */ } 5054}; 5055 5056static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 5057{ 5058 switch (pin) { 5059 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11): 5060 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 5061 return pin & 0x1f; 5062 5063 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10): 5064 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 5065 return (pin & 0x1f) + 19; 5066 5067 case PIN_VDDQ_AVB0: 5068 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; 5069 return 0; 5070 5071 default: 5072 return -EINVAL; 5073 } 5074} 5075 5076static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5077 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5078 [0] = RCAR_GP_PIN(2, 23), /* RD# */ 5079 [1] = RCAR_GP_PIN(2, 22), /* BS# */ 5080 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ 5081 [3] = PIN_AVB_MDC, /* AVB_MDC */ 5082 [4] = PIN_AVB_MDIO, /* AVB_MDIO */ 5083 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ 5084 [6] = PIN_AVB_TD3, /* AVB_TD3 */ 5085 [7] = PIN_AVB_TD2, /* AVB_TD2 */ 5086 [8] = PIN_AVB_TD1, /* AVB_TD1 */ 5087 [9] = PIN_AVB_TD0, /* AVB_TD0 */ 5088 [10] = PIN_AVB_TXC, /* AVB_TXC */ 5089 [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5090 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ 5091 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ 5092 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ 5093 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */ 5094 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */ 5095 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */ 5096 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */ 5097 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */ 5098 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */ 5099 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */ 5100 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */ 5101 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */ 5102 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */ 5103 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */ 5104 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */ 5105 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */ 5106 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */ 5107 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */ 5108 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */ 5109 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */ 5110 } }, 5111 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5112 [0] = RCAR_GP_PIN(0, 4), /* D4 */ 5113 [1] = RCAR_GP_PIN(0, 3), /* D3 */ 5114 [2] = RCAR_GP_PIN(0, 2), /* D2 */ 5115 [3] = RCAR_GP_PIN(0, 1), /* D1 */ 5116 [4] = RCAR_GP_PIN(0, 0), /* D0 */ 5117 [5] = RCAR_GP_PIN(1, 22), /* WE0# */ 5118 [6] = RCAR_GP_PIN(1, 21), /* CS0# */ 5119 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */ 5120 [8] = RCAR_GP_PIN(1, 19), /* A19 */ 5121 [9] = RCAR_GP_PIN(1, 18), /* A18 */ 5122 [10] = RCAR_GP_PIN(1, 17), /* A17 */ 5123 [11] = RCAR_GP_PIN(1, 16), /* A16 */ 5124 [12] = RCAR_GP_PIN(1, 15), /* A15 */ 5125 [13] = RCAR_GP_PIN(1, 14), /* A14 */ 5126 [14] = RCAR_GP_PIN(1, 13), /* A13 */ 5127 [15] = RCAR_GP_PIN(1, 12), /* A12 */ 5128 [16] = RCAR_GP_PIN(1, 11), /* A11 */ 5129 [17] = RCAR_GP_PIN(1, 10), /* A10 */ 5130 [18] = RCAR_GP_PIN(1, 9), /* A9 */ 5131 [19] = RCAR_GP_PIN(1, 8), /* A8 */ 5132 [20] = RCAR_GP_PIN(1, 7), /* A7 */ 5133 [21] = RCAR_GP_PIN(1, 6), /* A6 */ 5134 [22] = RCAR_GP_PIN(1, 5), /* A5 */ 5135 [23] = RCAR_GP_PIN(1, 4), /* A4 */ 5136 [24] = RCAR_GP_PIN(1, 3), /* A3 */ 5137 [25] = RCAR_GP_PIN(1, 2), /* A2 */ 5138 [26] = RCAR_GP_PIN(1, 1), /* A1 */ 5139 [27] = RCAR_GP_PIN(1, 0), /* A0 */ 5140 [28] = SH_PFC_PIN_NONE, 5141 [29] = SH_PFC_PIN_NONE, 5142 [30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */ 5143 [31] = RCAR_GP_PIN(2, 24), /* RD/WR# */ 5144 } }, 5145 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5146 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 5147 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 5148 [2] = PIN_ASEBRK, /* ASEBRK */ 5149 [3] = SH_PFC_PIN_NONE, 5150 [4] = PIN_TDI, /* TDI */ 5151 [5] = PIN_TMS, /* TMS */ 5152 [6] = PIN_TCK, /* TCK */ 5153 [7] = PIN_TRST_N, /* TRST# */ 5154 [8] = SH_PFC_PIN_NONE, 5155 [9] = SH_PFC_PIN_NONE, 5156 [10] = SH_PFC_PIN_NONE, 5157 [11] = SH_PFC_PIN_NONE, 5158 [12] = SH_PFC_PIN_NONE, 5159 [13] = SH_PFC_PIN_NONE, 5160 [14] = SH_PFC_PIN_NONE, 5161 [15] = PIN_FSCLKST_N, /* FSCLKST# */ 5162 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ 5163 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ 5164 [18] = SH_PFC_PIN_NONE, 5165 [19] = SH_PFC_PIN_NONE, 5166 [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5167 [21] = RCAR_GP_PIN(0, 15), /* D15 */ 5168 [22] = RCAR_GP_PIN(0, 14), /* D14 */ 5169 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5170 [24] = RCAR_GP_PIN(0, 12), /* D12 */ 5171 [25] = RCAR_GP_PIN(0, 11), /* D11 */ 5172 [26] = RCAR_GP_PIN(0, 10), /* D10 */ 5173 [27] = RCAR_GP_PIN(0, 9), /* D9 */ 5174 [28] = RCAR_GP_PIN(0, 8), /* D8 */ 5175 [29] = RCAR_GP_PIN(0, 7), /* D7 */ 5176 [30] = RCAR_GP_PIN(0, 6), /* D6 */ 5177 [31] = RCAR_GP_PIN(0, 5), /* D5 */ 5178 } }, 5179 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5180 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ 5181 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ 5182 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ 5183 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ 5184 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ 5185 [5] = SH_PFC_PIN_NONE, 5186 [6] = SH_PFC_PIN_NONE, 5187 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 5188 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 5189 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 5190 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 5191 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */ 5192 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */ 5193 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */ 5194 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */ 5195 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */ 5196 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */ 5197 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */ 5198 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */ 5199 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */ 5200 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */ 5201 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */ 5202 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 5203 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 5204 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 5205 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 5206 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 5207 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 5208 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 5209 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 5210 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 5211 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 5212 } }, 5213 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 5214 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */ 5215 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 5216 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 5217 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 5218 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 5219 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 5220 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 5221 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 5222 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 5223 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 5224 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 5225 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */ 5226 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */ 5227 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 5228 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 5229 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 5230 [16] = PIN_MLB_REF, /* MLB_REF */ 5231 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ 5232 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ 5233 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ 5234 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */ 5235 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */ 5236 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ 5237 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ 5238 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */ 5239 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */ 5240 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */ 5241 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */ 5242 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */ 5243 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */ 5244 [30] = RCAR_GP_PIN(5, 6), /* TX1 */ 5245 [31] = RCAR_GP_PIN(5, 5), /* RX1 */ 5246 } }, 5247 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 5248 [0] = SH_PFC_PIN_NONE, 5249 [1] = SH_PFC_PIN_NONE, 5250 [2] = SH_PFC_PIN_NONE, 5251 [3] = SH_PFC_PIN_NONE, 5252 [4] = SH_PFC_PIN_NONE, 5253 [5] = SH_PFC_PIN_NONE, 5254 [6] = SH_PFC_PIN_NONE, 5255 [7] = SH_PFC_PIN_NONE, 5256 [8] = SH_PFC_PIN_NONE, 5257 [9] = SH_PFC_PIN_NONE, 5258 [10] = SH_PFC_PIN_NONE, 5259 [11] = SH_PFC_PIN_NONE, 5260 [12] = SH_PFC_PIN_NONE, 5261 [13] = SH_PFC_PIN_NONE, 5262 [14] = SH_PFC_PIN_NONE, 5263 [15] = SH_PFC_PIN_NONE, 5264 [16] = SH_PFC_PIN_NONE, 5265 [17] = SH_PFC_PIN_NONE, 5266 [18] = SH_PFC_PIN_NONE, 5267 [19] = SH_PFC_PIN_NONE, 5268 [20] = SH_PFC_PIN_NONE, 5269 [21] = SH_PFC_PIN_NONE, 5270 [22] = SH_PFC_PIN_NONE, 5271 [23] = SH_PFC_PIN_NONE, 5272 [24] = SH_PFC_PIN_NONE, 5273 [25] = SH_PFC_PIN_NONE, 5274 [26] = SH_PFC_PIN_NONE, 5275 [27] = SH_PFC_PIN_NONE, 5276 [28] = SH_PFC_PIN_NONE, 5277 [29] = SH_PFC_PIN_NONE, 5278 [30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */ 5279 [31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */ 5280 } }, 5281 { /* sentinel */ } 5282}; 5283 5284static const struct sh_pfc_soc_operations r8a77990_pfc_ops = { 5285 .pin_to_pocctrl = r8a77990_pin_to_pocctrl, 5286 .get_bias = rcar_pinmux_get_bias, 5287 .set_bias = rcar_pinmux_set_bias, 5288}; 5289 5290#ifdef CONFIG_PINCTRL_PFC_R8A774C0 5291const struct sh_pfc_soc_info r8a774c0_pinmux_info = { 5292 .name = "r8a774c0_pfc", 5293 .ops = &r8a77990_pfc_ops, 5294 .unlock_reg = 0xe6060000, /* PMMR */ 5295 5296 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5297 5298 .pins = pinmux_pins, 5299 .nr_pins = ARRAY_SIZE(pinmux_pins), 5300 .groups = pinmux_groups.common, 5301 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 5302 .functions = pinmux_functions.common, 5303 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 5304 5305 .cfg_regs = pinmux_config_regs, 5306 .drive_regs = pinmux_drive_regs, 5307 .bias_regs = pinmux_bias_regs, 5308 .ioctrl_regs = pinmux_ioctrl_regs, 5309 5310 .pinmux_data = pinmux_data, 5311 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5312}; 5313#endif 5314 5315#ifdef CONFIG_PINCTRL_PFC_R8A77990 5316const struct sh_pfc_soc_info r8a77990_pinmux_info = { 5317 .name = "r8a77990_pfc", 5318 .ops = &r8a77990_pfc_ops, 5319 .unlock_reg = 0xe6060000, /* PMMR */ 5320 5321 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5322 5323 .pins = pinmux_pins, 5324 .nr_pins = ARRAY_SIZE(pinmux_pins), 5325 .groups = pinmux_groups.common, 5326 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 5327 ARRAY_SIZE(pinmux_groups.automotive), 5328 .functions = pinmux_functions.common, 5329 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 5330 ARRAY_SIZE(pinmux_functions.automotive), 5331 5332 .cfg_regs = pinmux_config_regs, 5333 .drive_regs = pinmux_drive_regs, 5334 .bias_regs = pinmux_bias_regs, 5335 .ioctrl_regs = pinmux_ioctrl_regs, 5336 5337 .pinmux_data = pinmux_data, 5338 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5339}; 5340#endif 5341