/u-boot/arch/arm/mach-nexell/include/mach/ |
H A D | clk.h | 11 unsigned long rate; member in struct:clk 19 long clk_round_rate(struct clk *clk, unsigned long rate); 20 int clk_set_rate(struct clk *clk, unsigned long rate);
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/u-boot/drivers/timer/ |
H A D | riscv_timer.c | 38 * timer_early_get_rate() - Get the timer rate before driver model 60 u32 rate; local 64 rate = timer_get_rate(gd->timer); 67 rate = RISCV_SMODE_TIMER_FREQ; 71 /* Below is converted from time(us) = (tick / rate) * 10000000 */ 72 return lldiv(ticks * 1000, (rate / 1000)); 79 u32 rate; local 84 rate = dev->driver_data; 86 /* When called from an FDT match, the rate needs to be looked up. */ 87 if (!rate [all...] |
/u-boot/arch/arm/mach-tegra/ |
H A D | emc.c | 26 unsigned rate; local 31 rate = EMC_SDRAM_RATE_T20; 34 rate = EMC_SDRAM_RATE_T25; 37 return tegra_set_emc(gd->fdt_blob, rate);
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/u-boot/include/ |
H A D | audio_codec.h | 24 * @rate: Sampling rate in Hz 30 int (*set_params)(struct udevice *dev, int interface, int rate, 41 * @rate: Sampling rate in Hz 47 int audio_codec_set_params(struct udevice *dev, int interface, int rate,
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H A D | tps6586x.h | 33 * @param rate Slew ratein mV/us: 0=instantly, 1=0.11, 2=0.22, 41 int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate,
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/u-boot/drivers/clk/renesas/ |
H A D | clk-rcar-gen2.c | 77 u32 value, mult, div, rate = 0; local 89 rate = gen2_clk_get_rate(&parent); 90 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", 91 __func__, __LINE__, parent.id, rate); 92 return rate; 102 rate = clk_get_rate(&priv->clk_extal); 103 debug("%s[%i] EXTAL clk: rate=%u\n", 104 __func__, __LINE__, rate); 105 return rate; 109 rate 204 gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate) argument 244 gen2_clk_set_rate(struct clk *clk, ulong rate) argument [all...] |
H A D | rcar-cpg-lib.c | 77 u64 rate; local 84 rate = parent_rate / div; 85 debug("%s[%i] %s clk: parent=%i div=%u => rate=%llu\n", 86 __func__, __LINE__, name, parent, div, rate); 88 return rate; 91 int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate, argument 97 div = DIV_ROUND_CLOSEST(parent_rate, rate); 104 debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%u\n", 105 __func__, __LINE__, name, parent, div, rate, value); 119 u64 rate local 148 rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate, void __iomem *reg) argument 162 rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate, void __iomem *reg) argument [all...] |
/u-boot/drivers/cpu/ |
H A D | at91_cpu.c | 81 ulong rate; local 88 rate = clk_get_rate(&clk); 89 if (!rate) 91 plat->cpufreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); 97 rate = clk_get_rate(&clk); 98 if (!rate) 100 plat->mckfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); 106 rate = clk_get_rate(&clk); 107 if (!rate) 109 plat->xtalfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 100000 [all...] |
/u-boot/arch/arm/mach-socfpga/ |
H A D | clock_manager_agilex.c | 24 ulong rate; local 38 rate = clk_get_rate(&clk); 40 if ((rate == (unsigned long)-ENOSYS) || 41 (rate == (unsigned long)-ENXIO) || 42 (rate == (unsigned long)-EIO)) { 44 __func__, id, rate); 48 return rate;
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H A D | clock_manager_agilex5.c | 33 ulong rate; local 47 rate = clk_get_rate(&clk); 49 if ((rate == (unsigned long)-ENOSYS) || 50 (rate == (unsigned long)-ENXIO) || 51 (rate == (unsigned long)-EIO)) { 53 __func__, id, rate); 57 return rate;
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H A D | clock_manager_n5x.c | 23 ulong rate; local 37 rate = clk_get_rate(&clk); 39 if ((rate == (unsigned long)-ENXIO) || 40 (rate == (unsigned long)-EIO)) { 42 __func__, id, rate); 46 return rate;
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/u-boot/drivers/clk/ti/ |
H A D | clk-am3-dpll-x2.c | 23 unsigned long rate; local 25 rate = clk_get_rate(&priv->parent); 26 if (IS_ERR_VALUE(rate)) 27 return rate; 29 rate *= 2; 30 dev_dbg(clk->dev, "rate=%ld\n", rate); 31 return rate;
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/u-boot/arch/arm/include/asm/kona-common/ |
H A D | clk.h | 21 long clk_round_rate(struct clk *clk, unsigned long rate); 22 int clk_set_rate(struct clk *clk, unsigned long rate); 25 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
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/u-boot/board/microchip/pic32mzda/ |
H A D | pic32mzda.c | 21 ulong rate; local 36 rate = clk_get_rate(&clk); 37 printf("CPU Speed: %lu MHz\n", rate / 1000000);
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/u-boot/test/dm/ |
H A D | audio.c | 18 int interface, rate, mclk_freq, bits_per_sample; local 25 sandbox_get_codec_params(dev, &interface, &rate, &mclk_freq, 28 ut_asserteq(2, rate);
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H A D | clk_ccf.c | 23 long long rate; local 47 rate = clk_get_parent_rate(clk); 48 ut_asserteq(rate, 20000000); 56 rate = clk_get_parent_rate(clk); 57 ut_asserteq(rate, 20000000); 65 rate = clk_get_parent_rate(clk); 66 ut_asserteq(rate, 60000000); 68 rate = clk_set_rate(clk, 60000000); 69 ut_asserteq(rate, -ENOSYS); 71 rate [all...] |
/u-boot/drivers/clk/rockchip/ |
H A D | clk_pll.c | 273 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) argument 277 while (rate_table->rate) { 278 if (rate_table->rate == rate) 282 if (rate_table->rate != rate) { 284 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); 286 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); 296 const struct rockchip_pll_rate_table *rate; local 298 rate 365 ulong rate; local 432 const struct rockchip_pll_rate_table *rate; local 551 u64 rate, postdiv; local 609 ulong rate = 0; local 661 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, ulong rate) argument [all...] |
H A D | clk_rk3568.c | 34 .rate = _rate##U, \ 98 ulong pll_id, ulong rate) 114 pmu_priv->pmucru, pll_id, rate); 207 ulong rate) 215 rational_best_approximation(rate, OSC_HZ, 244 ulong clk_id, ulong rate) 249 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); 288 ulong clk_id, ulong rate) 295 if (rate == OSC_HZ) { 302 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); 97 rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv, ulong pll_id, ulong rate) argument 206 rk3568_rtc32k_set_pmuclk(struct rk3568_pmuclk_priv *priv, ulong rate) argument 243 rk3568_i2c_set_pmuclk(struct rk3568_pmuclk_priv *priv, ulong clk_id, ulong rate) argument 287 rk3568_pwm_set_pmuclk(struct rk3568_pmuclk_priv *priv, ulong clk_id, ulong rate) argument 333 rk3568_pmu_set_pmuclk(struct rk3568_pmuclk_priv *priv, ulong rate) argument 353 ulong rate = 0; local 390 rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) argument 533 const struct rockchip_cpu_rate_table *rate; local 652 rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 716 u32 con, sel, rate; local 751 rk3568_bus_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 797 u32 con, sel, rate; local 831 rk3568_perimid_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 876 u32 con, sel, rate; local 934 rk3568_top_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1006 ulong rate; local 1032 rk3568_i2c_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1097 rk3568_spi_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1171 rk3568_pwm_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1234 rk3568_adc_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1339 rk3568_crypto_set_rate(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1443 rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1525 rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) argument 1573 rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate) argument 1627 rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate) argument 1685 rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) argument 1732 rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate) argument 1792 rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 1894 rk3568_gmac_src_set_clk(struct rk3568_clk_priv *priv, ulong mac_id, ulong rate) argument 1944 rk3568_gmac_out_set_clk(struct rk3568_clk_priv *priv, ulong mac_id, ulong rate) argument 1997 rk3568_gmac_ptp_ref_set_clk(struct rk3568_clk_priv *priv, ulong mac_id, ulong rate) argument 2027 rk3568_gmac_tx_rx_set_clk(struct rk3568_clk_priv *priv, ulong mac_id, ulong rate) argument 2082 rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate) argument 2135 rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 2246 rk3568_uart_set_rate(struct rk3568_clk_priv *priv, ulong clk_id, ulong rate) argument 2323 ulong rate = 0; local 2497 rk3568_clk_set_rate(struct clk *clk, ulong rate) argument [all...] |
H A D | clk_rk3588.c | 136 u32 con, sel, rate; 144 rate = 702 * MHz; 146 rate = 396 * MHz; 148 rate = 200 * MHz; 150 rate = OSC_HZ; 157 rate = 500 * MHz; 159 rate = 250 * MHz; 161 rate = 100 * MHz; 163 rate = OSC_HZ; 170 rate 126 u32 con, sel, rate; local 188 rk3588_center_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 258 u32 con, sel, div, rate, prate; local 300 rk3588_top_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 356 ulong rate; local 406 rk3588_i2c_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 500 rk3588_spi_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 584 rk3588_pwm_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 657 rk3588_adc_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 783 rk3588_mmc_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 890 rk3588_aux16m_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 969 rk3588_aclk_vop_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 1083 rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 1222 rk3588_gmac_set_clk(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 1324 rk3588_uart_set_rate(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 1433 rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv, ulong clk_id, ulong rate) argument 1477 ulong rate = 0; local 1644 rk3588_clk_set_rate(struct clk *clk, ulong rate) argument 2080 rk3588_scru_clk_set_rate(struct clk *clk, ulong rate) argument [all...] |
/u-boot/drivers/adc/ |
H A D | stm32-adc-core.h | 36 * @rate: clock rate used for analog circuitry 44 unsigned long rate; member in struct:stm32_adc_common
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/u-boot/arch/arm/mach-zynq/ |
H A D | clk.c | 26 ulong rate; local 40 rate = clk_get_rate(&clk) / 1000000; 42 gd->bd->bi_ddr_freq = rate; 44 gd->bd->bi_arm_freq = rate;
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/u-boot/arch/mips/mach-pic32/ |
H A D | cpu.c | 28 static ulong rate(int id) function 50 return rate(PB7CLK); 59 ulong rate; local 62 rate = clk_get_cpu_rate() / 1000000; 69 if (rate < 66) 71 else if (rate < 133) 76 if (rate <= 83) 78 else if (rate <= 166)
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/u-boot/drivers/sound/ |
H A D | codec-uclass.c | 13 int audio_codec_set_params(struct udevice *dev, int interface, int rate, argument 21 return ops->set_params(dev, interface, rate, mclk_freq, bits_per_sample,
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/u-boot/board/synopsys/hsdk/ |
H A D | clk-lib.c | 18 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) argument 42 if ((ctl & CLK_SET) && rate) { 43 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; 64 if ((ctl & CLK_GET) && rate) 65 *rate = priv_rate; 68 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate); 70 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate); 72 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);
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/u-boot/drivers/clk/ |
H A D | clk_fixed_factor.c | 28 uint64_t rate; local 31 rate = clk_get_rate(&ff->parent); 32 if (IS_ERR_VALUE(rate)) 33 return rate; 35 do_div(rate, ff->div); 37 return rate * ff->mult;
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