1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
4 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
5 * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
6 * Copyright (C) 2012 Regents of the University of California
7 *
8 * RISC-V architecturally-defined generic timer driver
9 *
10 * This driver provides generic timer support for S-mode U-Boot.
11 */
12
13#include <config.h>
14#include <div64.h>
15#include <dm.h>
16#include <errno.h>
17#include <fdt_support.h>
18#include <timer.h>
19#include <asm/csr.h>
20
21static u64 notrace riscv_timer_get_count(struct udevice *dev)
22{
23	__maybe_unused u32 hi, lo;
24
25	if (IS_ENABLED(CONFIG_64BIT))
26		return csr_read(CSR_TIME);
27
28	do {
29		hi = csr_read(CSR_TIMEH);
30		lo = csr_read(CSR_TIME);
31	} while (hi != csr_read(CSR_TIMEH));
32
33	return ((u64)hi << 32) | lo;
34}
35
36#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
37/**
38 * timer_early_get_rate() - Get the timer rate before driver model
39 */
40unsigned long notrace timer_early_get_rate(void)
41{
42	return RISCV_SMODE_TIMER_FREQ;
43}
44
45/**
46 * timer_early_get_count() - Get the timer count before driver model
47 *
48 */
49u64 notrace timer_early_get_count(void)
50{
51	return riscv_timer_get_count(NULL);
52}
53#endif
54
55#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
56ulong timer_get_boot_us(void)
57{
58	int ret;
59	u64 ticks = 0;
60	u32 rate;
61
62	ret = dm_timer_init();
63	if (!ret) {
64		rate = timer_get_rate(gd->timer);
65		timer_get_count(gd->timer, &ticks);
66	} else {
67		rate = RISCV_SMODE_TIMER_FREQ;
68		ticks = riscv_timer_get_count(NULL);
69	}
70
71	/* Below is converted from time(us) = (tick / rate) * 10000000 */
72	return lldiv(ticks * 1000, (rate / 1000));
73}
74#endif
75
76static int riscv_timer_probe(struct udevice *dev)
77{
78	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
79	u32 rate;
80
81	/*  When this function was called from the CPU driver, clock
82	 *  frequency is passed as driver data.
83	 */
84	rate = dev->driver_data;
85
86	/* When called from an FDT match, the rate needs to be looked up. */
87	if (!rate && gd->fdt_blob) {
88		rate = fdt_getprop_u32_default(gd->fdt_blob,
89					       "/cpus", "timebase-frequency", 0);
90	}
91
92	uc_priv->clock_rate = rate;
93
94	/* With rate==0, timer uclass post_probe might later fail with -EINVAL.
95	 * Give a hint at the cause for debugging.
96	 */
97	if (!rate)
98		log_err("riscv_timer_probe with invalid clock rate 0!\n");
99
100	return 0;
101}
102
103static const struct timer_ops riscv_timer_ops = {
104	.get_count = riscv_timer_get_count,
105};
106
107static const struct udevice_id riscv_timer_ids[] = {
108	{ .compatible = "riscv,timer", },
109	{ }
110};
111
112U_BOOT_DRIVER(riscv_timer) = {
113	.name = "riscv_timer",
114	.id = UCLASS_TIMER,
115	.of_match = of_match_ptr(riscv_timer_ids),
116	.probe = riscv_timer_probe,
117	.ops = &riscv_timer_ops,
118	.flags = DM_FLAG_PRE_RELOC,
119};
120