Searched refs:rank (Results 1 - 25 of 68) sorted by relevance

123

/u-boot/arch/x86/cpu/quark/
H A Dmrc_util.h85 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
87 void set_rcvn(uint8_t channel, uint8_t rank,
89 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
90 void set_rdqs(uint8_t channel, uint8_t rank,
92 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
93 void set_wdqs(uint8_t channel, uint8_t rank,
95 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
96 void set_wdq(uint8_t channel, uint8_t rank,
98 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
101 void set_wclk(uint8_t channel, uint8_t rank, uint32_
[all...]
H A Dmrc_util.c127 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) argument
130 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane);
136 * (currently doesn't comprehend rank)
138 void set_rcvn(uint8_t channel, uint8_t rank, argument
148 channel, rank, byte_lane, pi_count);
201 training_message(channel, rank, byte_lane);
210 * channel, rank, byte_lane as an absolute PI count.
212 * (currently doesn't comprehend rank)
214 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) argument
260 * (currently doesn't comprehend rank)
262 set_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane, uint32_t pi_count) argument
300 get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) argument
332 set_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane, uint32_t pi_count) argument
408 get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) argument
456 set_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane, uint32_t pi_count) argument
532 get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) argument
699 set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) argument
775 get_wclk(uint8_t channel, uint8_t rank) argument
820 set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) argument
894 get_wctl(uint8_t channel, uint8_t rank) argument
995 get_addr(uint8_t channel, uint8_t rank) argument
1023 sample_dqs(struct mrc_params *mrc_params, uint8_t channel, uint8_t rank, bool rcvn) argument
1090 find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], uint8_t channel, uint8_t rank, bool rcvn) argument
1378 print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank, uint8_t bl_divisor) argument
1448 uint8_t rank; local
[all...]
/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrphy-init.h13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
H A Dcmd_ddrphy.c142 int rank; local
146 for (rank = 0; rank < 4; rank++) {
147 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
148 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
165 int rank; local
169 for (rank = 0; rank < 4; rank
[all...]
H A Dcmd_ddrmphy.c168 int rank; local
172 for (rank = 0; rank < 4; rank++) {
173 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
174 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
191 int rank; local
195 for (rank = 0; rank < 4; rank
[all...]
H A Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) argument
29 /* Specify the rank that should be write leveled */
31 tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
38 /* Specify the rank used during data bit deskew and eye centering */
40 tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
43 /* Specify the rank enabled for data-training */
45 tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
/u-boot/board/rockchip/evb_rk3036/
H A Devb_rk3036.c16 config->rank = 2;
/u-boot/drivers/ram/rockchip/
H A Dsdram_pctl_px30.c14 * rank = 1: cs0
15 * rank = 2: cs1
17 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) argument
19 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);
28 /* rank = 1: cs0
29 * rank = 2: cs1
30 * rank = 3: cs0 & cs1
33 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, argument
39 writel((mr_num << 12) | (rank << 4) | (0 << 0),
43 writel((rank <<
62 pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, u32 dramtype) argument
[all...]
H A Dsdram_rk3188.c313 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, argument
316 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
323 u32 rank, u32 cmd, u32 ma, u32 op)
325 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
423 u32 rank; local
434 rank = sdram_params->ch[channel].rank | 1;
448 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
449 != rank)
451 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
322 send_command_op(struct rk3288_ddr_pctl *pctl, u32 rank, u32 cmd, u32 ma, u32 op) argument
[all...]
H A Dsdram_rk3066.c300 static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank, argument
303 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
310 u32 rank, u32 cmd, u32 ma, u32 op)
312 rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
408 u32 rank; local
419 rank = sdram_params->ch[channel].rank | 1;
433 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
434 != rank)
436 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
309 rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl, u32 rank, u32 cmd, u32 ma, u32 op) argument
[all...]
H A Dsdram_rk3288.c372 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, argument
375 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
382 u32 rank, u32 cmd, u32 ma, u32 op)
384 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
482 u32 rank; local
493 rank = sdram_params->ch[channel].rank | 1;
507 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
508 != rank)
510 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
381 send_command_op(struct rk3288_ddr_pctl *pctl, u32 rank, u32 cmd, u32 ma, u32 op) argument
[all...]
H A Dsdram_common.c69 if (cap_info->rank > 1) {
79 printdec(cap_info->rank);
158 if (cap_info->rank == 2)
193 *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel);
300 cs = cap_info->rank;
399 if (cap_info->rank == 2) {
H A Dsdram_rk3399.c84 int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank,
307 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
338 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
927 /* rank count need to set for init */
1033 u32 rank)
1043 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
1044 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
1045 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
1046 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
1086 u32 rank local
1032 select_per_cs_training_index(const struct chan_info *chan, u32 rank) argument
1152 u32 rank = params->ch[channel].cap_info.rank; local
1214 u32 rank = params->ch[channel].cap_info.rank; local
1276 u32 rank = params->ch[channel].cap_info.rank; local
1324 u32 rank = params->ch[channel].cap_info.rank; local
1628 data_training_first(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) argument
1769 read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank, u32 mr_num, u32 *buf) argument
1802 lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) argument
2907 int channel, ch, rank; local
[all...]
H A Dsdram-px30-ddr3-detect-333.inc4 .rank = 0x1,
H A Dsdram-px30-ddr4-detect-333.inc4 .rank = 0x1,
H A Dsdram-px30-lpddr2-detect-333.inc4 .rank = 0x1,
/u-boot/board/mntre/imx8mq_reform2/
H A Dlpddr4_timing_ch2.h48 #define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */
49 #define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */
57 #error unsupported memory rank/size
60 * rank0 will succeed, even if really rank 1, so we need
75 #error unsupported memory rank/size
85 #error unsupported rank bits
/u-boot/board/rockchip/kylin_rk3036/
H A Dkylin_rk3036.c19 config->rank = 1;
/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c27 u8 rank; member in struct:dram_para
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
49 u8 orig_rank = para->rank;
56 para->rank = 1;
73 para->rank = orig_rank;
151 /* Set two rank timing and exit self-refresh timing */
185 if (para->rank == 2)
231 /* Auto detect dram config, set 2 rank and 16bit bus-width */
233 para->rank = 2;
259 /* DRAM has only one rank */
[all...]
H A Ddram_sun8i_a83t.c25 u8 rank; member in struct:dram_para
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
48 u8 orig_rank = para->rank;
55 para->rank = 1;
72 para->rank = orig_rank;
183 /* Set two rank timing and exit self-refresh timing */
217 if (para->rank == 2)
314 /* Auto detect dram config, set 2 rank and 16bit bus-width */
316 para->rank = 2;
351 /* DRAM has only one rank */
[all...]
H A Ddram_sunxi_dw.c415 /* Mux pin to A15 address line for single rank memory. */
595 /* only one rank */
654 static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank) argument
657 rank->page_size = 512;
658 rank->row_bits = 16;
659 rank->bank_bits = 2;
662 for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++)
663 if (mctl_mem_matches_base((1 << (rank
683 mctl_calc_rank_size(struct rank_para *rank) argument
[all...]
H A Ddram_sun6i.c25 u8 rank; member in struct:dram_sun6i_para
92 static bool mctl_rank_detect(u32 *gsr0, int rank) argument
94 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
95 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
165 /* rank detect */
167 para->rank = 1;
172 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
181 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
275 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
340 .rank
[all...]
/u-boot/drivers/gpio/
H A Dlpc32xx_gpio.c111 int port, rank, mask, value; local
139 rank = GPIO_TO_RANK(offset);
142 return (value & mask) >> rank;
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3288.h17 u8 rank; member in struct:rk3288_sdram_channel
/u-boot/arch/arm/mach-rockchip/
H A Dsdram.c346 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; local
367 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
424 if (rank > 1)
430 if (rank > 1)
431 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
433 rank, cs0_col, cs1_col, bk, cs0_row,
436 debug("rank %d cs0_col %d bk %d cs0_row %d\
438 rank, cs0_col, bk, cs0_row,

Completed in 416 milliseconds

123