1/* SPDX-License-Identifier: Intel */
2/*
3 * Copyright (C) 2013, Intel Corporation
4 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 *
6 * Ported from Intel released Quark UEFI BIOS
7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8 */
9
10#ifndef _MRC_UTIL_H_
11#define _MRC_UTIL_H_
12
13#include <log.h>
14
15/* Turn on this macro to enable MRC debugging output */
16#undef  MRC_DEBUG
17
18/* MRC Debug Support */
19#define DPF		debug_cond
20
21/* debug print type */
22
23#ifdef MRC_DEBUG
24#define D_ERROR		0x0001
25#define D_INFO		0x0002
26#define D_REGRD		0x0004
27#define D_REGWR		0x0008
28#define D_FCALL		0x0010
29#define D_TRN		0x0020
30#define D_TIME		0x0040
31#else
32#define D_ERROR		0
33#define D_INFO		0
34#define D_REGRD		0
35#define D_REGWR		0
36#define D_FCALL		0
37#define D_TRN		0
38#define D_TIME		0
39#endif
40
41#define ENTERFN(...)	debug_cond(D_FCALL, "<%s>\n", __func__)
42#define LEAVEFN(...)	debug_cond(D_FCALL, "</%s>\n", __func__)
43#define REPORTFN(...)	debug_cond(D_FCALL, "<%s/>\n", __func__)
44
45/* Message Bus Port */
46#define MEM_CTLR	0x01
47#define HOST_BRIDGE	0x03
48#define MEM_MGR		0x05
49#define HTE		0x11
50#define DDRPHY		0x12
51
52/* number of sample points */
53#define SAMPLE_CNT	3
54/* number of PIs to increment per sample */
55#define SAMPLE_DLY	26
56
57enum {
58	/* indicates to decrease delays when looking for edge */
59	BACKWARD,
60	/* indicates to increase delays when looking for edge */
61	FORWARD
62};
63
64enum {
65	RCVN,
66	WDQS,
67	WDQX,
68	RDQS,
69	VREF,
70	WCMD,
71	WCTL,
72	WCLK,
73	MAX_ALGOS,
74};
75
76void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
77void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
78void mrc_post_code(uint8_t major, uint8_t minor);
79void delay_n(uint32_t ns);
80void delay_u(uint32_t ms);
81void select_mem_mgr(void);
82void select_hte(void);
83void dram_init_command(uint32_t data);
84void dram_wake_command(void);
85void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
86
87void set_rcvn(uint8_t channel, uint8_t rank,
88	      uint8_t byte_lane, uint32_t pi_count);
89uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
90void set_rdqs(uint8_t channel, uint8_t rank,
91	      uint8_t byte_lane, uint32_t pi_count);
92uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
93void set_wdqs(uint8_t channel, uint8_t rank,
94	      uint8_t byte_lane, uint32_t pi_count);
95uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
96void set_wdq(uint8_t channel, uint8_t rank,
97	     uint8_t byte_lane, uint32_t pi_count);
98uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
99void set_wcmd(uint8_t channel, uint32_t pi_count);
100uint32_t get_wcmd(uint8_t channel);
101void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
102uint32_t get_wclk(uint8_t channel, uint8_t rank);
103void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
104uint32_t get_wctl(uint8_t channel, uint8_t rank);
105void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
106uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
107
108uint32_t get_addr(uint8_t channel, uint8_t rank);
109uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
110		    uint8_t rank, bool rcvn);
111void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
112		      uint8_t channel, uint8_t rank, bool rcvn);
113uint32_t byte_lane_mask(struct mrc_params *mrc_params);
114uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
115uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
116void lfsr32(uint32_t *lfsr_ptr);
117void clear_pointers(void);
118void print_timings(struct mrc_params *mrc_params);
119
120#endif /* _MRC_UTIL_H_ */
121