/u-boot/drivers/usb/host/ |
H A D | ehci-mx6.c | 199 void __iomem *phy_ctrl; local 203 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 218 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 222 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 228 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 238 void __iomem *phy_ctrl; local 242 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 244 val = readl(phy_ctrl); 513 void *__iomem phy_ctrl, *__iomem phy_status; local 534 phy_ctrl [all...] |
H A D | ehci-vf.c | 90 void __iomem *phy_ctrl; local 94 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 107 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 111 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 118 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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/u-boot/arch/arm/mach-exynos/ |
H A D | dmc_init_ddr3.c | 278 * @param phy_ctrl pointer to the current phy controller 281 *phy_ctrl) 283 return readl(&phy_ctrl->phy_con4); 289 * @param phy_ctrl pointer to the current phy controller 291 static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) argument 293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); 294 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); 302 * @param phy_ctrl pointer to the current phy controller 305 static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, argument 308 writel(offset, &phy_ctrl 280 dmc_get_read_offset_value(struct exynos5420_phy_control *phy_ctrl) argument 351 test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, int start, int end, int results[NUM_BYTE_LANES]) argument 402 software_find_read_offset(struct exynos5420_phy_control *phy_ctrl, int ch, unsigned int coarse_lock_val) argument [all...] |
/u-boot/arch/arm/include/asm/arch-aspeed/ |
H A D | sdram_ast2500.h | 120 u32 phy_ctrl[4]; member in struct:ast2500_sdrammc_regs
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H A D | sdram_ast2600.h | 156 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member in struct:ast2600_sdrammc_regs
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/u-boot/drivers/ram/aspeed/ |
H A D | sdram_ast2500.c | 99 writel(0, ®s->phy_ctrl[0]); 102 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 103 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) 106 ®s->phy_ctrl[0]); 111 writel(0, &info->regs->phy_ctrl[0]);
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H A D | sdram_ast2600.c | 559 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 561 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 565 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 588 writel(0, &info->regs->phy_ctrl[0]);
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/u-boot/drivers/net/ |
H A D | e1000.c | 2386 uint32_t phy_ctrl = 0; local 2408 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2426 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2427 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2478 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2479 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2521 uint32_t phy_ctrl = 0; local 2530 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2532 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2542 phy_ctrl [all...] |
/u-boot/drivers/ram/ |
H A D | k3-am654-ddrss.c | 207 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; 1016 (u32 *)&ddrss->params.phy_ctrl, 1017 sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
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H A D | k3-am654-ddrss.h | 1194 struct ddrss_ddrphy_ctrl_params phy_ctrl; member in struct:ddrss_params
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/u-boot/arch/arm/mach-exynos/include/mach/ |
H A D | dp.h | 192 unsigned int phy_ctrl; member in struct:exynos_dp
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/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-pcieepx-defs.h | 6717 u32 phy_ctrl : 32; member in struct:cvmx_pcieepx_cfg517::cvmx_pcieepx_cfg517_s
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H A D | cvmx-pciercx-defs.h | 5455 u32 phy_ctrl : 32; member in struct:cvmx_pciercx_cfg517::cvmx_pciercx_cfg517_s
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